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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?utf-8?q?ysqQi/KLWnsNz/Z1K+HYmMLPq/hd?= =?utf-8?q?GC6VS6MzRWz+3+vQK0PeyV8QK72dta36vPXmS5G38N5x/rKgttF7fCtFtj//jtBdU?= =?utf-8?q?hyObhXbzAHLN6uSQJTZEs2XR/HsDtbImBMu50DKbiqTDsbXpdIfKKBNG+t3LVWUd8?= =?utf-8?q?FzbU6ib1OBuR30cKpU74ZqIh4xg8V13QffLKUJG9CndrMqRtr2AR7IZ8Dh86LCZOH?= =?utf-8?q?9NBPM7+TNSbNvSsXvy59zfPtDB+2mLlTDyD1dulkoPqMqDLv3k2FmQiKbCr4P+tzf?= =?utf-8?q?c/ZgU9pVF93gA9VRSLtzFZLGe1UNvcHLvyrs26BfjtWJ1yHek//uLPdF3lG1UB794?= =?utf-8?q?8QtGAUpViiKh86JPuD0dewrDnZp5QWNkQAIcVvrrlRVBn8EejpzZpEnTuiLjoCkVa?= =?utf-8?q?c8o9GkbiIY79gLuR6g7s+O9qQgU4kQcKRWephy/FxoLB1XCedhatOVGyU8ydlwC3X?= =?utf-8?q?xrftDFKxlHn+O0nrHLvnJRa2HhSRH6PW8Q51qmIIg5hYe2EnKiHmi7eaIvqU+6F9X?= =?utf-8?q?diC/P6WJwLgtQXdOS43d2HQJeKbZCAyC0BDz+dvr1Hyg2P0VjaWkaYfQ9QWt+B8Ji?= =?utf-8?q?pPVdRdVusSk4VWSZTAM1EiHkAwycxrXMjBLSx7Pv1N3xDh0rrodlTj28zRf3rFku3?= =?utf-8?q?/TXgC95I4CFOYj0RX/IDuiwzAMXUs2GczJdhrftjqWIneir5K+1y7JI5w6BJp+Ko5?= =?utf-8?q?j3w2Nz3Sr8OcYUdcvSzh0pkjltL6+SMITcV7IbnWW6B+DGTHZtMeIhO52M9xjIZFx?= =?utf-8?q?sOjZ3Mbc5ZsfY6SijUPhTUHuMKKEv2VJmjxwR5D+Oy9WEZcOptJ3hngBFC0leUB1g?= =?utf-8?q?1YcqaHeLcpTzvPBI3SJWhYuotBat4QZdjgDCC53ro/aa45rjGj49u9cWwMFRTHKbH?= =?utf-8?q?du3JgCptxz0EiBYNHbBzFKjN+ZAnhVYyBleopCUf4CV4mKst+h5FPEow9CITo5nl+?= =?utf-8?q?mUVY4ZRmJyaNuG+ZxXyexPvJ98AvMVfUNtcW94bC3zvqY+AOZ2OUSbmReP2CId/4b?= =?utf-8?q?AYyqLIZvXzwK7ATNXDJOj+GuoUC5tURypIwHJYfvaXYa+pEKAcqAt1UnmRFx+pajK?= =?utf-8?q?WU/k4ZE1LYqFirYcZGURnD2OiWCWWBsQ5X5VyVmiD5ome7HffLz2EoqauG9OBgfao?= =?utf-8?q?fSLncOoIM+ratRh80VEf21sDXvHi88imnrVpiz5/Ryou5PFIvCT1qa5vtpIJ+HIxs?= =?utf-8?q?M7O7CPyOqescORWican/o2CN+Kd2noLgfk5y7s8rQukZv/cwMHCKW3yvE7s0OQ77/?= =?utf-8?q?vXwQHmCoJ4jd4YaAliKclISwwfCcb2eM0Z87sQJU4ABaqZQNWrwowWN6y7qvvSkhg?= =?utf-8?q?Yh8bXdmgyz+SSj04ywiBrlX5cg307BrSbyCuIxdVhxOQXIWkYfSPkz2W+zmO1Y52A?= =?utf-8?q?uW/jS/RmaVb2oLLNAhgt7hHuJ9ug/wtBMpw+A4MpPoxUtcOtLV9Yss3QJmA9Q1phz?= =?utf-8?q?zV4VKoH9Nx+ZhsruzHee3gSfMJ/9LYSxLi2vknvUpBPJHuKGngXvDyNx4fUwHexBK?= =?utf-8?q?hqDjSxbwzfqO?= X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: 5a22b166-c021-440c-0476-08dc482eb230 X-MS-Exchange-CrossTenant-AuthSource: PAXPR04MB9642.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 19 Mar 2024 16:07:37.5746 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: R46hvF2TaVw+0IEzDGXeKahGUFt5AdE9nNbpC4sL4mUNGc8dhhJ7aDX+iqKmCQfvhaA8YUteO6HxGioOux9nww== X-MS-Exchange-Transport-CrossTenantHeadersStamped: DBBPR04MB7772 Reserve space at end of first IORESOURCE_MEM window as message TLP MMIO window. This space's size is 'region_align'. Set outbound ATU map memory write to send PCI message. So one MMIO write can trigger a PCI message, such as PME_Turn_Off. Add common dwc_pme_turn_off() function. Call dwc_pme_turn_off() to send out PME_Turn_Off message in general dw_pcie_suspend_noirq() if there are not platform callback pme_turn_off() exist. Signed-off-by: Frank Li --- drivers/pci/controller/dwc/pcie-designware-host.c | 94 ++++++++++++++++++++++- drivers/pci/controller/dwc/pcie-designware.h | 3 + 2 files changed, 93 insertions(+), 4 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c index 267687ab33cbc..d5723fce7a894 100644 --- a/drivers/pci/controller/dwc/pcie-designware-host.c +++ b/drivers/pci/controller/dwc/pcie-designware-host.c @@ -393,6 +393,31 @@ static int dw_pcie_msi_host_init(struct dw_pcie_rp *pp) return 0; } +static void dw_pcie_host_request_msg_tlp_res(struct dw_pcie_rp *pp) +{ + struct dw_pcie *pci = to_dw_pcie_from_pp(pp); + struct resource_entry *win; + struct resource *res; + + win = resource_list_first_type(&pp->bridge->windows, IORESOURCE_MEM); + if (win) { + res = devm_kzalloc(pci->dev, sizeof(*res), GFP_KERNEL); + if (!res) + return; + + /* Reserve last region_align block as message TLP space */ + res->start = win->res->end - pci->region_align + 1; + res->end = win->res->end; + res->name = "msg"; + res->flags = win->res->flags | IORESOURCE_BUSY; + + if (!request_resource(win->res, res)) + pp->msg_res = res; + else + devm_kfree(pci->dev, res); + } +} + int dw_pcie_host_init(struct dw_pcie_rp *pp) { struct dw_pcie *pci = to_dw_pcie_from_pp(pp); @@ -479,6 +504,10 @@ int dw_pcie_host_init(struct dw_pcie_rp *pp) dw_pcie_iatu_detect(pci); + /* Need call after dw_pcie_iatu_detect() before dw_pcie_setup_rc() */ + if (pp->use_atu_msg) + dw_pcie_host_request_msg_tlp_res(pp); + ret = dw_pcie_edma_detect(pci); if (ret) goto err_free_msi; @@ -536,6 +565,11 @@ void dw_pcie_host_deinit(struct dw_pcie_rp *pp) dw_pcie_edma_remove(pci); + if (pp->msg_res) { + release_resource(pp->msg_res); + devm_kfree(pci->dev, pp->msg_res); + } + if (pp->has_msi_ctrl) dw_pcie_free_msi(pp); @@ -697,6 +731,10 @@ static int dw_pcie_iatu_setup(struct dw_pcie_rp *pp) atu.pci_addr = entry->res->start - entry->offset; atu.size = resource_size(entry->res); + /* MSG TLB window resource reserve at one of end of IORESOURCE_MEM resource */ + if (pp->msg_res && pp->msg_res->parent == entry->res) + atu.size -= resource_size(pp->msg_res); + ret = dw_pcie_prog_outbound_atu(pci, &atu); if (ret) { dev_err(pci->dev, "Failed to set MEM range %pr\n", @@ -728,6 +766,8 @@ static int dw_pcie_iatu_setup(struct dw_pcie_rp *pp) dev_warn(pci->dev, "Ranges exceed outbound iATU size (%d)\n", pci->num_ob_windows); + pp->msg_atu_index = i; + i = 0; resource_list_for_each_entry(entry, &pp->bridge->dma_ranges) { if (resource_type(entry->res) != IORESOURCE_MEM) @@ -833,11 +873,54 @@ int dw_pcie_setup_rc(struct dw_pcie_rp *pp) } EXPORT_SYMBOL_GPL(dw_pcie_setup_rc); +/* Using message outbound ATU to send out PME_Turn_Off message for dwc PCIe controller */ +static int dw_pcie_pme_turn_off(struct dw_pcie *pci) +{ + struct dw_pcie_ob_atu_cfg atu = { 0 }; + void __iomem *m; + int ret; + + if (pci->num_ob_windows <= pci->pp.msg_atu_index) + return -EINVAL; + + if (!pci->pp.msg_res) + return -EINVAL; + + atu.code = PCIE_MSG_CODE_PME_TURN_OFF; + atu.routing = PCIE_MSG_TYPE_R_BC; + atu.type = PCIE_ATU_TYPE_MSG; + atu.size = resource_size(pci->pp.msg_res); + atu.index = pci->pp.msg_atu_index; + + if (!atu.size) { + dev_dbg(pci->dev, + "atu memory map windows is zero, please check 'msg' reg in dts\n"); + return -ENOMEM; + } + + atu.cpu_addr = pci->pp.msg_res->start; + + ret = dw_pcie_prog_outbound_atu(pci, &atu); + if (ret) + return ret; + + m = ioremap(atu.cpu_addr, pci->region_align); + if (!m) + return -ENOMEM; + + /* A dummy write is converted to a Msg TLP */ + writel(0, m); + + iounmap(m); + + return 0; +} + int dw_pcie_suspend_noirq(struct dw_pcie *pci) { u8 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); u32 val; - int ret; + int ret = 0; /* * If L1SS is supported, then do not put the link into L2 as some @@ -849,10 +932,13 @@ int dw_pcie_suspend_noirq(struct dw_pcie *pci) if (dw_pcie_get_ltssm(pci) <= DW_PCIE_LTSSM_DETECT_ACT) return 0; - if (!pci->pp.ops->pme_turn_off) - return 0; + if (pci->pp.ops->pme_turn_off) + pci->pp.ops->pme_turn_off(&pci->pp); + else + ret = dw_pcie_pme_turn_off(pci); - pci->pp.ops->pme_turn_off(&pci->pp); + if (ret) + return ret; ret = read_poll_timeout(dw_pcie_get_ltssm, val, val == DW_PCIE_LTSSM_L2_IDLE, PCIE_PME_TO_L2_TIMEOUT_US/10, diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h index 703b50bc5e0f1..dca5de4c6e877 100644 --- a/drivers/pci/controller/dwc/pcie-designware.h +++ b/drivers/pci/controller/dwc/pcie-designware.h @@ -341,6 +341,9 @@ struct dw_pcie_rp { struct pci_host_bridge *bridge; raw_spinlock_t lock; DECLARE_BITMAP(msi_irq_in_use, MAX_MSI_IRQS); + bool use_atu_msg; + int msg_atu_index; + struct resource *msg_res; }; struct dw_pcie_ep_ops {