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b=NnZhO5eN95ogikvzrG3mSb8tAkydQZZLyN2xe4umDw4Q9udb82czKFiSs7IQy1x6EtjybkFhtehp0S9+gHm9pWvrUBixgWEPnXxms2o1yOctIK7mbwtEetQNaLWY/OxW2mqtGqVa1YhRlDq9gRE3gpzdpPbt8f+6JL/OysDDOl8= Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=nxp.com; Received: from PAXPR04MB8829.eurprd04.prod.outlook.com (2603:10a6:102:20c::17) by DB9PR04MB8091.eurprd04.prod.outlook.com (2603:10a6:10:245::7) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7409.15; Fri, 22 Mar 2024 06:39:20 +0000 Received: from PAXPR04MB8829.eurprd04.prod.outlook.com ([fe80::1b13:505:8d50:f4e3]) by PAXPR04MB8829.eurprd04.prod.outlook.com ([fe80::1b13:505:8d50:f4e3%4]) with mapi id 15.20.7386.023; Fri, 22 Mar 2024 06:39:20 +0000 From: Xu Yang To: frank.li@nxp.com, will@kernel.org, mark.rutland@arm.com, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, shawnguo@kernel.org, s.hauer@pengutronix.de, kernel@pengutronix.de, festevam@gmail.com, john.g.garry@oracle.com, jolsa@kernel.org, namhyung@kernel.org, irogers@google.com Cc: mike.leach@linaro.org, peterz@infradead.org, mingo@redhat.com, acme@kernel.org, alexander.shishkin@linux.intel.com, adrian.hunter@intel.com, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, imx@lists.linux.dev Subject: [PATCH v8 2/8] perf: imx_perf: add macro definitions for parsing config attr Date: Fri, 22 Mar 2024 14:39:24 +0800 Message-Id: <20240322063930.749126-2-xu.yang_2@nxp.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240322063930.749126-1-xu.yang_2@nxp.com> References: <20240322063930.749126-1-xu.yang_2@nxp.com> X-ClientProxiedBy: SG2PR02CA0121.apcprd02.prod.outlook.com (2603:1096:4:188::21) To PAXPR04MB8829.eurprd04.prod.outlook.com (2603:10a6:102:20c::17) Precedence: bulk X-Mailing-List: imx@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: PAXPR04MB8829:EE_|DB9PR04MB8091:EE_ X-MS-Office365-Filtering-Correlation-Id: d1b1523b-065e-4dc2-02d8-08dc4a3acdb9 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: TYOHe1uXIqkosnjq0qduxw+dF1Gi+RiO78W6S0P4ntQvK7Cfkk8hDrh2kyU3dPJpjhko5O0jT0EpZ0S8CuuJW1QQlMBXUkQqpXW/mhESdi5c34YUpmcJ75Y47i7p/eneWVLfw1TK2yIlvUGrb2w0jwUhKY9rd+fWjsbTb1lZwewStzkpTxSkoIq09pcs21mt/tLq1rFFZOgeUTctZ30KbgYh8iCtLD1w7al+3ndEIE4rxF3yXsgoRRYmVt20x6smVTRQVZZjmtzzqaq4i2rKFoQwFUWjY11bm4dl19iZLU/uUTQas1SFeAQcKZBsacX+nUPdZjmiUH+zzjjgZt+yQgcTuij7Vw+BsbY1IgvzvZTZfgDdZffZ6bLxXqkQlmt/R+q0ZYS6IJ8flFAoRula3mIDKFN2831Qlv2pnXS5THJShYjHKyWeG8htOvL3tEzRcOgYrForXDYpiwqc2VEgO34G2hi6tY0CKyLnP9FSBoaeYDzfPc7eSH1mkAz0VK/UsdAxobftDyhgkGewo8u5yEoicnwgYaRTNSj2DP1gJoNet94gIDTCZOIcWSqxZ+sHfhgD/lSWbk8LNKtADlMUJO74mNSf221mYcxmOkpU61gp0aYHu3DQEwomlp4pQ66g45ZdSuan5uo5CebPN8GMyAUea4zizb3PJlaohsAa3doSGE5XOfqzewvlvFhKMd1yIbHpYhy8aUl18Dc/kAP1ryz+rfVSrV9u8yMJlHOzJ0ZmDEvjjwDu90Pe11FWI7XzJT/I2DKBMudGSpWogh1DuNTAu6XoHhdLGQLixZFqmKsu2ZtgGUB6Mipwf2ilThTLvvlNnPVgA+3IjY3fjefy/FmTp9pQAmsuRR7lXFnFQhMLwvNjy9NGOOGarScG9SeNHedsQaN69s8iUX79ixIWpfQtzNwmFSFjv9NAOqGD16YdDZ3VnUMYa7CLeJSi50ZFuSmi8N89StCweH1kGta9iVEHmUOUzol+GwfY7Da7i4z6DeiswFJN2y0t/AQQNPfSEhPhYo/OuwGsUH+XWhq38U0Fm4LcHNcSZZE517G09O9ma8UpHycdI4SS7VlgoPQvlQo7y/FnEUUMQFfXbwmg/6EXS59aUE09UQmpw2llJpUhxdQL0m+78pX1LZRTrcrszmzzVYcGXDojMaL8MWw4/Y6mudvaDpw0UY6YSRvWdDXaCmxFld6snu7jynZpYMfYR3R61vB6c/azko5jKRXNcgPCxbrkR1qnKYI0iQ4E1zVLmC9mGc4gHrmD8nbktEvd8ySRW7KpXhJ/kRJpvaMsZlJFoGhcVECrpuCBZRxTAE5fkrXa8htW9GTGqljFp+VC/IXaUsKPF+xNvreoJDZXMqqMMRxkufnrOMb2qICG87Mx1kQTKXfp568937NR+BMVw9/f9x77URKxTbCWeRW9GdqaowYCrk4uzn7Qc8zB4JtFL7ltFA3hDXVJVt5OJBT3TK+cTJ71Y1Xv2NGKG0GU1Zv3tfWEzNmWu8+4ER7XZCgYYpxn1XrE1EHYQBGESZQ7vb+Dso9JAagLk15XUDrV5ka3ssrhj4Ydv9GmJEiWPKe4DO6anAlt+HEXc+t9caD+ X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: d1b1523b-065e-4dc2-02d8-08dc4a3acdb9 X-MS-Exchange-CrossTenant-AuthSource: PAXPR04MB8829.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 22 Mar 2024 06:39:20.1660 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: 010S2OVnLjJR032Zgc61Ojld3m1EFj6yYgOMLHNGS2Bqt/A9XXfIJ0Xm1+E7JWWQo9V6yF/9CN8BZRTgnwkODA== X-MS-Exchange-Transport-CrossTenantHeadersStamped: DB9PR04MB8091 The user can set event and counter in cmdline and the driver need to parse it using 'config' attr value. This will add macro definitions to avoid hard-code in driver. Reviewed-by: Frank Li Signed-off-by: Xu Yang --- Changes in v4: - new patch Changes in v5: - move this patch earlier Changes in v6: - no changes Changes in v7: - use FIELD_* Changes in v8: - add Rb tag --- drivers/perf/fsl_imx9_ddr_perf.c | 13 +++++++++---- 1 file changed, 9 insertions(+), 4 deletions(-) diff --git a/drivers/perf/fsl_imx9_ddr_perf.c b/drivers/perf/fsl_imx9_ddr_perf.c index 72c2d3074cde..0017f2c9ef91 100644 --- a/drivers/perf/fsl_imx9_ddr_perf.c +++ b/drivers/perf/fsl_imx9_ddr_perf.c @@ -42,6 +42,9 @@ #define NUM_COUNTERS 11 #define CYCLES_COUNTER 0 +#define CONFIG_EVENT GENMASK(7, 0) +#define CONFIG_COUNTER GENMASK(15, 8) + #define to_ddr_pmu(p) container_of(p, struct ddr_pmu, pmu) #define DDR_PERF_DEV_NAME "imx9_ddr" @@ -339,8 +342,10 @@ static void ddr_perf_counter_local_config(struct ddr_pmu *pmu, int config, int counter, bool enable) { u32 ctrl_a; + int event; ctrl_a = readl_relaxed(pmu->base + PMLCA(counter)); + event = FIELD_GET(CONFIG_EVENT, config); if (enable) { ctrl_a |= PMLCA_FC; @@ -352,7 +357,7 @@ static void ddr_perf_counter_local_config(struct ddr_pmu *pmu, int config, ctrl_a &= ~PMLCA_FC; ctrl_a |= PMLCA_CE; ctrl_a &= ~FIELD_PREP(PMLCA_EVENT, 0x7F); - ctrl_a |= FIELD_PREP(PMLCA_EVENT, (config & 0x000000FF)); + ctrl_a |= FIELD_PREP(PMLCA_EVENT, event); writel(ctrl_a, pmu->base + PMLCA(counter)); } else { /* Freeze counter. */ @@ -366,8 +371,8 @@ static void ddr_perf_monitor_config(struct ddr_pmu *pmu, int cfg, int cfg1, int u32 pmcfg1, pmcfg2; int event, counter; - event = cfg & 0x000000FF; - counter = (cfg & 0x0000FF00) >> 8; + event = FIELD_GET(CONFIG_EVENT, cfg); + counter = FIELD_GET(CONFIG_COUNTER, cfg); pmcfg1 = readl_relaxed(pmu->base + PMCFG1); @@ -469,7 +474,7 @@ static int ddr_perf_event_add(struct perf_event *event, int flags) int cfg2 = event->attr.config2; int counter; - counter = (cfg & 0x0000FF00) >> 8; + counter = FIELD_GET(CONFIG_COUNTER, cfg); pmu->events[counter] = event; pmu->active_events++;