From patchwork Mon May 27 21:24:37 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andy Shevchenko X-Patchwork-Id: 13675883 Received: from fgw20-7.mail.saunalahti.fi (fgw20-7.mail.saunalahti.fi [62.142.5.81]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 76A7F16191B for ; Mon, 27 May 2024 21:27:53 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=62.142.5.81 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1716845275; cv=none; b=WqQ82nAvddyKdpsJpyMxB2jwblmL1c23BAliaRLzivhPBkxQo8x5xuZQpjlofc61pKUMHP6vyTIV84mqBh3NkJqnCQxc/jXcB+VHNEarDpJ50cuhp1rrZsWrbjJ7D1aa0SL2nsSB+drn/KPLFbS7IHv44zLl/d4d9F+LBz7T+Mg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1716845275; c=relaxed/simple; bh=IG9NOQLA1NVT/Pr565vBNzMxxl6QNt3PXh2uJqn55B8=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=teeYurJvKtRCyYRZzbCqWiPLF34x6DuDYzF5m8l9UrWuTbZEPK1sSYhaOO/5u6YHdAafL0Sw3XRBxM1jRkEcFR2fmGecfunmcwM3tSY3wLz8bzB8w7i2fmnEVxqJ4u/YKN4Hm4Y5SxVyQa+4RSD0PatJOW5h4hUcMlreTLjbGPM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=fail (p=none dis=none) header.from=gmail.com; spf=fail smtp.mailfrom=gmail.com; arc=none smtp.client-ip=62.142.5.81 Authentication-Results: smtp.subspace.kernel.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=gmail.com Received: from localhost (88-113-26-230.elisa-laajakaista.fi [88.113.26.230]) by fgw21.mail.saunalahti.fi (Halon) with ESMTP id f7ebd5e0-1c6f-11ef-aaf3-005056bdd08f; Tue, 28 May 2024 00:27:50 +0300 (EEST) From: Andy Shevchenko To: Andy Shevchenko , Linus Walleij , linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-mips@vger.kernel.org Cc: Dong Aisheng , Fabio Estevam , Shawn Guo , Jacky Bai , Pengutronix Kernel Team , Sascha Hauer , Sean Wang , Matthias Brugger , AngeloGioacchino Del Regno , Paul Cercueil , Lakshmi Sowjanya D , Andy Shevchenko Subject: [PATCH v1 02/11] pinctrl: equilibrium: Make use of struct pinfunction Date: Tue, 28 May 2024 00:24:37 +0300 Message-ID: <20240527212742.1432960-3-andy.shevchenko@gmail.com> X-Mailer: git-send-email 2.45.1 In-Reply-To: <20240527212742.1432960-1-andy.shevchenko@gmail.com> References: <20240527212742.1432960-1-andy.shevchenko@gmail.com> Precedence: bulk X-Mailing-List: imx@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Andy Shevchenko Since pin control provides a generic data type for the pin function, use it in the driver. Signed-off-by: Andy Shevchenko --- drivers/pinctrl/pinctrl-equilibrium.c | 18 +++++++++--------- drivers/pinctrl/pinctrl-equilibrium.h | 12 ------------ 2 files changed, 9 insertions(+), 21 deletions(-) diff --git a/drivers/pinctrl/pinctrl-equilibrium.c b/drivers/pinctrl/pinctrl-equilibrium.c index 6e1be38865c3..9eb1859add11 100644 --- a/drivers/pinctrl/pinctrl-equilibrium.c +++ b/drivers/pinctrl/pinctrl-equilibrium.c @@ -566,8 +566,8 @@ static const struct pinconf_ops eqbr_pinconf_ops = { .pin_config_config_dbg_show = pinconf_generic_dump_config, }; -static bool is_func_exist(struct eqbr_pmx_func *funcs, const char *name, - unsigned int nr_funcs, unsigned int *idx) +static bool is_func_exist(struct pinfunction *funcs, const char *name, + unsigned int nr_funcs, unsigned int *idx) { int i; @@ -584,7 +584,7 @@ static bool is_func_exist(struct eqbr_pmx_func *funcs, const char *name, return false; } -static int funcs_utils(struct device *dev, struct eqbr_pmx_func *funcs, +static int funcs_utils(struct device *dev, struct pinfunction *funcs, unsigned int *nr_funcs, funcs_util_ops op) { struct device_node *node = dev->of_node; @@ -620,12 +620,12 @@ static int funcs_utils(struct device *dev, struct eqbr_pmx_func *funcs, case OP_COUNT_NR_FUNC_GRPS: if (is_func_exist(funcs, fn_name, *nr_funcs, &fid)) - funcs[fid].nr_groups++; + funcs[fid].ngroups++; break; case OP_ADD_FUNC_GRPS: if (is_func_exist(funcs, fn_name, *nr_funcs, &fid)) { - for (j = 0; j < funcs[fid].nr_groups; j++) + for (j = 0; j < funcs[fid].ngroups; j++) if (!funcs[fid].groups[j]) break; funcs[fid].groups[j] = prop->value; @@ -645,7 +645,7 @@ static int funcs_utils(struct device *dev, struct eqbr_pmx_func *funcs, static int eqbr_build_functions(struct eqbr_pinctrl_drv_data *drvdata) { struct device *dev = drvdata->dev; - struct eqbr_pmx_func *funcs = NULL; + struct pinfunction *funcs = NULL; unsigned int nr_funcs = 0; int i, ret; @@ -666,9 +666,9 @@ static int eqbr_build_functions(struct eqbr_pinctrl_drv_data *drvdata) return ret; for (i = 0; i < nr_funcs; i++) { - if (!funcs[i].nr_groups) + if (!funcs[i].ngroups) continue; - funcs[i].groups = devm_kcalloc(dev, funcs[i].nr_groups, + funcs[i].groups = devm_kcalloc(dev, funcs[i].ngroups, sizeof(*(funcs[i].groups)), GFP_KERNEL); if (!funcs[i].groups) @@ -688,7 +688,7 @@ static int eqbr_build_functions(struct eqbr_pinctrl_drv_data *drvdata) ret = pinmux_generic_add_function(drvdata->pctl_dev, funcs[i].name, funcs[i].groups, - funcs[i].nr_groups, + funcs[i].ngroups, drvdata); if (ret < 0) { dev_err(dev, "Failed to register function %s\n", diff --git a/drivers/pinctrl/pinctrl-equilibrium.h b/drivers/pinctrl/pinctrl-equilibrium.h index 83768cc8b3db..b4d149bde39d 100644 --- a/drivers/pinctrl/pinctrl-equilibrium.h +++ b/drivers/pinctrl/pinctrl-equilibrium.h @@ -67,18 +67,6 @@ struct gpio_irq_type { unsigned int logic_type; }; -/** - * struct eqbr_pmx_func: represent a pin function. - * @name: name of the pin function, used to lookup the function. - * @groups: one or more names of pin groups that provide this function. - * @nr_groups: number of groups included in @groups. - */ -struct eqbr_pmx_func { - const char *name; - const char **groups; - unsigned int nr_groups; -}; - /** * struct eqbr_pin_bank: represent a pin bank. * @membase: base address of the pin bank register.