From patchwork Thu Jun 6 09:01:55 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Walle X-Patchwork-Id: 13688084 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D3908154C15; Thu, 6 Jun 2024 09:02:26 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1717664546; cv=none; b=A0ZuJV9UWZ2eZZo/GowvUUVBlk/czwYRZTjz0gC2KWAgBNXHzVrTGC4UsFBt5059KeQuTs9KahyWUcufkse2PHrEZiWTdEeoeV9Xmi0+FPGyhv+9HSvwu4Y4ZJREH/jeNuzJZufNUoyiPaB23D1myAZmVWWtYC2eGu9TbIuxGlE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1717664546; c=relaxed/simple; bh=2Qw+7Rve50c6UoNrfytgIz8RzG/OQfuJ1xjLwlqspyo=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=DGcWLeysvGCBH8+9WnZzIIgo3tMVVjVGCLHYp9UAxWXGI9wNLe01Ax00/Egs+2Jp+nzhJNQgduRd6oMzV0Ak91HUDFhNMTsF4VQFbC15eKVQ7ZME1uXQv9ZIg6Gi5QK18nHWmMyxLFUhAr3Y2Aslohq8M2NLWbhJ+RzM/Sv//I4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=S2d+6eBj; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="S2d+6eBj" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 64E1AC4AF07; Thu, 6 Jun 2024 09:02:23 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1717664546; bh=2Qw+7Rve50c6UoNrfytgIz8RzG/OQfuJ1xjLwlqspyo=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=S2d+6eBjZ5kP68dFSj0TZzIf77aFWFvjtoO4cL7KOZjFtNAa8JqtPRCvHkvK4iZnE vvx2fZriKpWQIVmjfo8nTCZ8rGtkvcOodMqnpuOe3JVTwtW3LXMGaQN50RjKg+7QFW 0ABben+eHgityInCqu19O+/vV19lW5kqNXt7Pfm1fr9rhkaaCOJqzxh9lvB0/HAy1q rHj7PZe1Wfjo+brqxERA5hVzduUe+niEyIt8EBer0jdhkmxlapUlYWGIT5Q27Dcl64 C1j7Pdv6bMcD2Grt14K70TuNakWIk7Pre9VnvxqOGq1YsdbhOKDFiVqjOkv1Fohser WDZn/ZHBD6W7A== From: Michael Walle To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Shawn Guo , Sascha Hauer , Li Yang Cc: Pengutronix Kernel Team , Fabio Estevam , Priit Laes , Michael Grzeschik , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Marco Felsch , imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, Michael Walle Subject: [PATCH v2 02/13] ARM: dts: imx6qdl-kontron-samx6i: fix PHY reset Date: Thu, 6 Jun 2024 11:01:55 +0200 Message-Id: <20240606090206.2021237-3-mwalle@kernel.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240606090206.2021237-1-mwalle@kernel.org> References: <20240606090206.2021237-1-mwalle@kernel.org> Precedence: bulk X-Mailing-List: imx@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 The PHY reset line is connected to both the SoC (GPIO1_25) and the CPLD. We must not use the GPIO1_25 as it will drive against the output buffer of the CPLD. Instead there is another GPIO (GPIO2_01), an input to the CPLD, which will tell the CPLD to assert the PHY reset line. Fixes: 2a51f9dae13d ("ARM: dts: imx6qdl-kontron-samx6i: Add iMX6-based Kontron SMARC-sAMX6i module") Fixes: 5694eed98cca ("ARM: dts: imx6qdl-kontron-samx6i: move phy reset into phy-node") Signed-off-by: Michael Walle --- arch/arm/boot/dts/nxp/imx/imx6qdl-kontron-samx6i.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-kontron-samx6i.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-kontron-samx6i.dtsi index d8c1dfb8c9ab..d6c049b9a9c6 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6qdl-kontron-samx6i.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-kontron-samx6i.dtsi @@ -269,7 +269,7 @@ mdio { ethphy: ethernet-phy@1 { compatible = "ethernet-phy-ieee802.3-c22"; reg = <1>; - reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>; + reset-gpios = <&gpio2 1 GPIO_ACTIVE_LOW>; reset-assert-us = <1000>; }; }; @@ -516,7 +516,7 @@ MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 - MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x1b0b0 /* RST_GBE0_PHY# */ + MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b0b0 /* RST_GBE0_PHY# */ >; };