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[1/1] dt-bindings: clock: qoriq-clock: convert to yaml format

Message ID 20240617181410.921090-1-Frank.Li@nxp.com (mailing list archive)
State Superseded
Headers show
Series [1/1] dt-bindings: clock: qoriq-clock: convert to yaml format | expand

Commit Message

Frank Li June 17, 2024, 6:14 p.m. UTC
Convert qoria-clock DT binding to yaml format. Split to two files
qoriq-clock.yaml and qoriq-clock-legancy.yaml.

Addtional change:
- Remove clock consumer part in example
- Fixed example dts error
- Deprecated legancy node

Signed-off-by: Frank Li <Frank.Li@nxp.com>
---
 .../clock/fsl,qoriq-clock-legacy.yaml         |  84 +++++++
 .../bindings/clock/fsl,qoriq-clock.yaml       | 203 +++++++++++++++++
 .../devicetree/bindings/clock/qoriq-clock.txt | 212 ------------------
 3 files changed, 287 insertions(+), 212 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/clock/fsl,qoriq-clock-legacy.yaml
 create mode 100644 Documentation/devicetree/bindings/clock/fsl,qoriq-clock.yaml
 delete mode 100644 Documentation/devicetree/bindings/clock/qoriq-clock.txt

Comments

Rob Herring (Arm) June 27, 2024, 8:22 p.m. UTC | #1
On Mon, Jun 17, 2024 at 02:14:09PM -0400, Frank Li wrote:
> Convert qoria-clock DT binding to yaml format. Split to two files
> qoriq-clock.yaml and qoriq-clock-legancy.yaml.
> 
> Addtional change:
> - Remove clock consumer part in example
> - Fixed example dts error
> - Deprecated legancy node
> 
> Signed-off-by: Frank Li <Frank.Li@nxp.com>
> ---
>  .../clock/fsl,qoriq-clock-legacy.yaml         |  84 +++++++
>  .../bindings/clock/fsl,qoriq-clock.yaml       | 203 +++++++++++++++++
>  .../devicetree/bindings/clock/qoriq-clock.txt | 212 ------------------
>  3 files changed, 287 insertions(+), 212 deletions(-)
>  create mode 100644 Documentation/devicetree/bindings/clock/fsl,qoriq-clock-legacy.yaml
>  create mode 100644 Documentation/devicetree/bindings/clock/fsl,qoriq-clock.yaml
>  delete mode 100644 Documentation/devicetree/bindings/clock/qoriq-clock.txt
> 
> diff --git a/Documentation/devicetree/bindings/clock/fsl,qoriq-clock-legacy.yaml b/Documentation/devicetree/bindings/clock/fsl,qoriq-clock-legacy.yaml
> new file mode 100644
> index 0000000000000..97b96a1a58254
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/clock/fsl,qoriq-clock-legacy.yaml
> @@ -0,0 +1,84 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/clock/fsl,qoriq-clock-legacy.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Legacy Clock Block on Freescale QorIQ Platforms
> +
> +maintainers:
> +  - Frank Li <Frank.Li@nxp.com>
> +
> +description: |
> +  These nodes are deprecated.  Kernels should continue to support
> +  device trees with these nodes, but new device trees should not use them.
> +
> +  Most of the bindings are from the common clock binding[1].
> +  [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
> +
> +properties:
> +  compatible:
> +    enum:
> +      - fsl,qoriq-core-pll-1.0
> +      - fsl,qoriq-core-pll-2.0
> +      - fsl,qoriq-core-mux-1.0
> +      - fsl,qoriq-core-mux-2.0
> +      - fsl,qoriq-sysclk-1.0
> +      - fsl,qoriq-sysclk-2.0
> +      - fsl,qoriq-platform-pll-1.0
> +      - fsl,qoriq-platform-pll-2.0
> +
> +  reg:
> +    maxItems: 1
> +
> +  clocks:
> +    minItems: 1
> +    maxItems: 4
> +
> +  clock-names:
> +    minItems: 1
> +    maxItems: 4
> +
> +  clock-output-names:
> +    minItems: 1
> +    maxItems: 8
> +
> +  '#clock-cells':
> +    minimum: 0
> +    maximum: 1
> +
> +required:
> +  - compatible
> +  - '#clock-cells'
> +
> +additionalProperties: false
> +
> +allOf:
> +  - if:
> +      properties:
> +        compatible:
> +          contains:
> +            enum:
> +              - fsl,qoriq-sysclk-1.0
> +              - fsl,qoriq-sysclk-2.0
> +    then:
> +      properties:
> +        '#clock-cells':
> +          const: 0
> +
> +  - if:
> +      properties:
> +        compatible:
> +          contains:
> +            enum:
> +              - fsl,qoriq-core-pll-1.0
> +              - fsl,qoriq-core-pll-2.0
> +    then:
> +      properties:
> +        '#clock-cells':
> +          const: 1
> +          description: |
> +            * 0 - equal to the PLL frequency
> +            * 1 - equal to the PLL frequency divided by 2
> +            * 2 - equal to the PLL frequency divided by 4
> +
> diff --git a/Documentation/devicetree/bindings/clock/fsl,qoriq-clock.yaml b/Documentation/devicetree/bindings/clock/fsl,qoriq-clock.yaml
> new file mode 100644
> index 0000000000000..d641756b04635
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/clock/fsl,qoriq-clock.yaml
> @@ -0,0 +1,203 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/clock/fsl,qoriq-clock.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Clock Block on Freescale QorIQ Platforms
> +
> +maintainers:
> +  - Frank Li <Frank.Li@nxp.com>
> +
> +

Just 1 blank line

> +description: |
> +

drop blank line

> +  Freescale QorIQ chips take primary clocking input from the external
> +  SYSCLK signal. The SYSCLK input (frequency) is multiplied using
> +  multiple phase locked loops (PLL) to create a variety of frequencies
> +  which can then be passed to a variety of internal logic, including
> +  cores and peripheral IP blocks.
> +  Please refer to the Reference Manual for details.
> +
> +  All references to "1.0" and "2.0" refer to the QorIQ chassis version to
> +  which the chip complies.
> +
> +  Chassis Version    Example Chips
> +  ---------------    -------------
> +       1.0      p4080, p5020, p5040
> +       2.0      t4240, b4860
> +
> +  Clock Provider
> +
> +  The clockgen node should act as a clock provider, though in older device
> +  trees the children of the clockgen node are the clock providers.
> +
> +properties:
> +  compatible:
> +    items:
> +      - enum:
> +          - fsl,p2041-clockgen
> +          - fsl,p3041-clockgen
> +          - fsl,p4080-clockgen
> +          - fsl,p5020-clockgen
> +          - fsl,p5040-clockgen
> +          - fsl,t1023-clockgen
> +          - fsl,t1024-clockgen
> +          - fsl,t1040-clockgen
> +          - fsl,t1042-clockgen
> +          - fsl,t2080-clockgen
> +          - fsl,t2081-clockgen
> +          - fsl,t4240-clockgen
> +          - fsl,b4420-clockgen
> +          - fsl,b4860-clockgen

> +          - fsl,ls1012a-clockgen
> +          - fsl,ls1021a-clockgen
> +          - fsl,ls1028a-clockgen
> +          - fsl,ls1043a-clockgen
> +          - fsl,ls1046a-clockgen
> +          - fsl,ls1088a-clockgen
> +          - fsl,ls2080a-clockgen
> +          - fsl,lx2160a-clockgen

It doesn't look to me like these platforms use this binding.

> +      - enum:
> +          - fsl,qoriq-clockgen-1.0
> +          - fsl,qoriq-clockgen-2.0

This allows invalid combinations. You need 2 entries splitting 1.0 and 
2.0.

> +    minItems: 1
> +
> +  reg:
> +    maxItems: 1
> +
> +  ranges: true
> +
> +  '#address-cells':
> +    const: 1
> +
> +  '#size-cells':
> +    const: 1
> +
> +  '#clock-cells':
> +    const: 2
> +    description: |
> +      The first cell of the clock specifier is the clock type, and the
> +      second cell is the clock index for the specified type.
> +
> +        Type#  Name       Index Cell
> +        0  sysclk          must be 0
> +        1  cmux            index (n in CLKCnCSR)
> +        2  hwaccel         index (n in CLKCGnHWACSR)
> +        3  fman            0 for fm1, 1 for fm2
> +        4  platform pll    n=pll/(n+1). For example, when n=1,
> +                          that means output_freq=PLL_freq/2.
> +        5  coreclk         must be 0
> +
> +  clock-frequency:
> +    description: Input system clock frequency (SYSCLK)
> +
> +  clocks:
> +    items:
> +      - description:
> +          sysclk may be provided as an input clock.  Either clock-frequency
> +          or clocks must be provided.
> +      - description:
> +          A second input clock, called "coreclk", may be provided if
> +          core PLLs are based on a different input clock from the
> +          platform PLL.
> +    minItems: 1
> +
> +  clock-names:
> +    items:
> +      - const: sysclk
> +      - const: coreclk
> +
> +patternProperties:
> +  '^mux[0-9]@[a-f0-9]+$':
> +    deprecated: true
> +    $ref: fsl,qoriq-clock-legacy.yaml
> +
> +  '^sysclk+$':

This means 'sysclkkkkkkkkkk' is valid.

> +    deprecated: true
> +    $ref: fsl,qoriq-clock-legacy.yaml
> +
> +  '^pll[0-9]@[a-f0-9]+$':
> +    deprecated: true
> +    $ref: fsl,qoriq-clock-legacy.yaml
> +
> +  '^platform\-pll@[a-f0-9]+$':
> +    deprecated: true
> +    $ref: fsl,qoriq-clock-legacy.yaml
> +
> +required:
> +  - compatible
> +  - reg
> +  - '#clock-cells'
> +
> +additionalProperties: false
> +
> +examples:
> +  - |
> +    /* clock provider example */
> +    global-utilities@e1000 {
> +        compatible = "fsl,p5020-clockgen", "fsl,qoriq-clockgen-1.0";
> +        reg = <0xe1000 0x1000>;
> +        clock-frequency = <133333333>;
> +        #clock-cells = <2>;
> +    };
> +
> +  - |
> +    /* Legacy example */
> +    global-utilities@e1000 {
> +        compatible = "fsl,p5020-clockgen", "fsl,qoriq-clockgen-1.0";
> +        reg = <0xe1000 0x1000>;
> +        ranges = <0x0 0xe1000 0x1000>;
> +        clock-frequency = <133333333>;
> +        #address-cells = <1>;
> +        #size-cells = <1>;
> +        #clock-cells = <2>;
> +
> +        sysclk: sysclk {
> +            compatible = "fsl,qoriq-sysclk-1.0";
> +            clock-output-names = "sysclk";
> +            #clock-cells = <0>;
> +        };
> +
> +        pll0: pll0@800 {
> +            compatible = "fsl,qoriq-core-pll-1.0";
> +            reg = <0x800 0x4>;
> +            #clock-cells = <1>;
> +            clocks = <&sysclk>;
> +            clock-output-names = "pll0", "pll0-div2";
> +        };
> +
> +        pll1: pll1@820 {
> +            compatible = "fsl,qoriq-core-pll-1.0";
> +            reg = <0x820 0x4>;
> +            #clock-cells = <1>;
> +            clocks = <&sysclk>;
> +            clock-output-names = "pll1", "pll1-div2";
> +        };
> +
> +        mux0: mux0@0 {
> +            compatible = "fsl,qoriq-core-mux-1.0";
> +            reg = <0x0 0x4>;
> +            #clock-cells = <0>;
> +            clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
> +            clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
> +            clock-output-names = "cmux0";
> +        };
> +
> +        mux1: mux1@20 {
> +            compatible = "fsl,qoriq-core-mux-1.0";
> +            reg = <0x20 0x4>;
> +            #clock-cells = <0>;
> +            clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
> +            clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
> +            clock-output-names = "cmux1";
> +        };
> +
> +        platform-pll@c00 {
> +            #clock-cells = <1>;
> +            reg = <0xc00 0x4>;
> +            compatible = "fsl,qoriq-platform-pll-1.0";
> +            clocks = <&sysclk>;
> +            clock-output-names = "platform-pll", "platform-pll-div2";
> +        };
> +    };
Frank Li June 28, 2024, 8:44 p.m. UTC | #2
On Thu, Jun 27, 2024 at 02:22:54PM -0600, Rob Herring wrote:
> On Mon, Jun 17, 2024 at 02:14:09PM -0400, Frank Li wrote:
> > Convert qoria-clock DT binding to yaml format. Split to two files
> > qoriq-clock.yaml and qoriq-clock-legancy.yaml.
> > 
> > Addtional change:
> > - Remove clock consumer part in example
> > - Fixed example dts error
> > - Deprecated legancy node
> > 
> > Signed-off-by: Frank Li <Frank.Li@nxp.com>
> > ---
> >  .../clock/fsl,qoriq-clock-legacy.yaml         |  84 +++++++
> >  .../bindings/clock/fsl,qoriq-clock.yaml       | 203 +++++++++++++++++
> >  .../devicetree/bindings/clock/qoriq-clock.txt | 212 ------------------
> >  3 files changed, 287 insertions(+), 212 deletions(-)
> >  create mode 100644 Documentation/devicetree/bindings/clock/fsl,qoriq-clock-legacy.yaml
> >  create mode 100644 Documentation/devicetree/bindings/clock/fsl,qoriq-clock.yaml
> >  delete mode 100644 Documentation/devicetree/bindings/clock/qoriq-clock.txt
> > 
> > diff --git a/Documentation/devicetree/bindings/clock/fsl,qoriq-clock-legacy.yaml b/Documentation/devicetree/bindings/clock/fsl,qoriq-clock-legacy.yaml
> > new file mode 100644
> > index 0000000000000..97b96a1a58254
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/clock/fsl,qoriq-clock-legacy.yaml
> > @@ -0,0 +1,84 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/clock/fsl,qoriq-clock-legacy.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: Legacy Clock Block on Freescale QorIQ Platforms
> > +
> > +maintainers:
> > +  - Frank Li <Frank.Li@nxp.com>
> > +
> > +description: |
> > +  These nodes are deprecated.  Kernels should continue to support
> > +  device trees with these nodes, but new device trees should not use them.
> > +
> > +  Most of the bindings are from the common clock binding[1].
> > +  [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
> > +
> > +properties:
> > +  compatible:
> > +    enum:
> > +      - fsl,qoriq-core-pll-1.0
> > +      - fsl,qoriq-core-pll-2.0
> > +      - fsl,qoriq-core-mux-1.0
> > +      - fsl,qoriq-core-mux-2.0
> > +      - fsl,qoriq-sysclk-1.0
> > +      - fsl,qoriq-sysclk-2.0
> > +      - fsl,qoriq-platform-pll-1.0
> > +      - fsl,qoriq-platform-pll-2.0
> > +
> > +  reg:
> > +    maxItems: 1
> > +
> > +  clocks:
> > +    minItems: 1
> > +    maxItems: 4
> > +
> > +  clock-names:
> > +    minItems: 1
> > +    maxItems: 4
> > +
> > +  clock-output-names:
> > +    minItems: 1
> > +    maxItems: 8
> > +
> > +  '#clock-cells':
> > +    minimum: 0
> > +    maximum: 1
> > +
> > +required:
> > +  - compatible
> > +  - '#clock-cells'
> > +
> > +additionalProperties: false
> > +
> > +allOf:
> > +  - if:
> > +      properties:
> > +        compatible:
> > +          contains:
> > +            enum:
> > +              - fsl,qoriq-sysclk-1.0
> > +              - fsl,qoriq-sysclk-2.0
> > +    then:
> > +      properties:
> > +        '#clock-cells':
> > +          const: 0
> > +
> > +  - if:
> > +      properties:
> > +        compatible:
> > +          contains:
> > +            enum:
> > +              - fsl,qoriq-core-pll-1.0
> > +              - fsl,qoriq-core-pll-2.0
> > +    then:
> > +      properties:
> > +        '#clock-cells':
> > +          const: 1
> > +          description: |
> > +            * 0 - equal to the PLL frequency
> > +            * 1 - equal to the PLL frequency divided by 2
> > +            * 2 - equal to the PLL frequency divided by 4
> > +
> > diff --git a/Documentation/devicetree/bindings/clock/fsl,qoriq-clock.yaml b/Documentation/devicetree/bindings/clock/fsl,qoriq-clock.yaml
> > new file mode 100644
> > index 0000000000000..d641756b04635
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/clock/fsl,qoriq-clock.yaml
> > @@ -0,0 +1,203 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/clock/fsl,qoriq-clock.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: Clock Block on Freescale QorIQ Platforms
> > +
> > +maintainers:
> > +  - Frank Li <Frank.Li@nxp.com>
> > +
> > +
> 
> Just 1 blank line
> 
> > +description: |
> > +
> 
> drop blank line
> 
> > +  Freescale QorIQ chips take primary clocking input from the external
> > +  SYSCLK signal. The SYSCLK input (frequency) is multiplied using
> > +  multiple phase locked loops (PLL) to create a variety of frequencies
> > +  which can then be passed to a variety of internal logic, including
> > +  cores and peripheral IP blocks.
> > +  Please refer to the Reference Manual for details.
> > +
> > +  All references to "1.0" and "2.0" refer to the QorIQ chassis version to
> > +  which the chip complies.
> > +
> > +  Chassis Version    Example Chips
> > +  ---------------    -------------
> > +       1.0      p4080, p5020, p5040
> > +       2.0      t4240, b4860
> > +
> > +  Clock Provider
> > +
> > +  The clockgen node should act as a clock provider, though in older device
> > +  trees the children of the clockgen node are the clock providers.
> > +
> > +properties:
> > +  compatible:
> > +    items:
> > +      - enum:
> > +          - fsl,p2041-clockgen
> > +          - fsl,p3041-clockgen
> > +          - fsl,p4080-clockgen
> > +          - fsl,p5020-clockgen
> > +          - fsl,p5040-clockgen
> > +          - fsl,t1023-clockgen
> > +          - fsl,t1024-clockgen
> > +          - fsl,t1040-clockgen
> > +          - fsl,t1042-clockgen
> > +          - fsl,t2080-clockgen
> > +          - fsl,t2081-clockgen
> > +          - fsl,t4240-clockgen
> > +          - fsl,b4420-clockgen
> > +          - fsl,b4860-clockgen
> 
> > +          - fsl,ls1012a-clockgen
> > +          - fsl,ls1021a-clockgen
> > +          - fsl,ls1028a-clockgen
> > +          - fsl,ls1043a-clockgen
> > +          - fsl,ls1046a-clockgen
> > +          - fsl,ls1088a-clockgen
> > +          - fsl,ls2080a-clockgen
> > +          - fsl,lx2160a-clockgen
> 
> It doesn't look to me like these platforms use this binding.

It should be used.

git grep -r "a\-clockgen" arch/arm64/

arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi:                 compatible = "fsl,ls1012a-clockgen";
arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi:                 compatible = "fsl,ls1028a-clockgen";
arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi:                 compatible = "fsl,ls1043a-clockgen";
arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi:                 compatible = "fsl,ls1046a-clockgen";
arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi:                 compatible = "fsl,ls1088a-clockgen";
arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi:                 compatible = "fsl,ls2080a-clockgen";
arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi:                 compatible = "fsl,lx2160a-clockgen";

Frank

> 
> > +      - enum:
> > +          - fsl,qoriq-clockgen-1.0
> > +          - fsl,qoriq-clockgen-2.0
> 
> This allows invalid combinations. You need 2 entries splitting 1.0 and 
> 2.0.
> 
> > +    minItems: 1
> > +
> > +  reg:
> > +    maxItems: 1
> > +
> > +  ranges: true
> > +
> > +  '#address-cells':
> > +    const: 1
> > +
> > +  '#size-cells':
> > +    const: 1
> > +
> > +  '#clock-cells':
> > +    const: 2
> > +    description: |
> > +      The first cell of the clock specifier is the clock type, and the
> > +      second cell is the clock index for the specified type.
> > +
> > +        Type#  Name       Index Cell
> > +        0  sysclk          must be 0
> > +        1  cmux            index (n in CLKCnCSR)
> > +        2  hwaccel         index (n in CLKCGnHWACSR)
> > +        3  fman            0 for fm1, 1 for fm2
> > +        4  platform pll    n=pll/(n+1). For example, when n=1,
> > +                          that means output_freq=PLL_freq/2.
> > +        5  coreclk         must be 0
> > +
> > +  clock-frequency:
> > +    description: Input system clock frequency (SYSCLK)
> > +
> > +  clocks:
> > +    items:
> > +      - description:
> > +          sysclk may be provided as an input clock.  Either clock-frequency
> > +          or clocks must be provided.
> > +      - description:
> > +          A second input clock, called "coreclk", may be provided if
> > +          core PLLs are based on a different input clock from the
> > +          platform PLL.
> > +    minItems: 1
> > +
> > +  clock-names:
> > +    items:
> > +      - const: sysclk
> > +      - const: coreclk
> > +
> > +patternProperties:
> > +  '^mux[0-9]@[a-f0-9]+$':
> > +    deprecated: true
> > +    $ref: fsl,qoriq-clock-legacy.yaml
> > +
> > +  '^sysclk+$':
> 
> This means 'sysclkkkkkkkkkk' is valid.
> 
> > +    deprecated: true
> > +    $ref: fsl,qoriq-clock-legacy.yaml
> > +
> > +  '^pll[0-9]@[a-f0-9]+$':
> > +    deprecated: true
> > +    $ref: fsl,qoriq-clock-legacy.yaml
> > +
> > +  '^platform\-pll@[a-f0-9]+$':
> > +    deprecated: true
> > +    $ref: fsl,qoriq-clock-legacy.yaml
> > +
> > +required:
> > +  - compatible
> > +  - reg
> > +  - '#clock-cells'
> > +
> > +additionalProperties: false
> > +
> > +examples:
> > +  - |
> > +    /* clock provider example */
> > +    global-utilities@e1000 {
> > +        compatible = "fsl,p5020-clockgen", "fsl,qoriq-clockgen-1.0";
> > +        reg = <0xe1000 0x1000>;
> > +        clock-frequency = <133333333>;
> > +        #clock-cells = <2>;
> > +    };
> > +
> > +  - |
> > +    /* Legacy example */
> > +    global-utilities@e1000 {
> > +        compatible = "fsl,p5020-clockgen", "fsl,qoriq-clockgen-1.0";
> > +        reg = <0xe1000 0x1000>;
> > +        ranges = <0x0 0xe1000 0x1000>;
> > +        clock-frequency = <133333333>;
> > +        #address-cells = <1>;
> > +        #size-cells = <1>;
> > +        #clock-cells = <2>;
> > +
> > +        sysclk: sysclk {
> > +            compatible = "fsl,qoriq-sysclk-1.0";
> > +            clock-output-names = "sysclk";
> > +            #clock-cells = <0>;
> > +        };
> > +
> > +        pll0: pll0@800 {
> > +            compatible = "fsl,qoriq-core-pll-1.0";
> > +            reg = <0x800 0x4>;
> > +            #clock-cells = <1>;
> > +            clocks = <&sysclk>;
> > +            clock-output-names = "pll0", "pll0-div2";
> > +        };
> > +
> > +        pll1: pll1@820 {
> > +            compatible = "fsl,qoriq-core-pll-1.0";
> > +            reg = <0x820 0x4>;
> > +            #clock-cells = <1>;
> > +            clocks = <&sysclk>;
> > +            clock-output-names = "pll1", "pll1-div2";
> > +        };
> > +
> > +        mux0: mux0@0 {
> > +            compatible = "fsl,qoriq-core-mux-1.0";
> > +            reg = <0x0 0x4>;
> > +            #clock-cells = <0>;
> > +            clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
> > +            clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
> > +            clock-output-names = "cmux0";
> > +        };
> > +
> > +        mux1: mux1@20 {
> > +            compatible = "fsl,qoriq-core-mux-1.0";
> > +            reg = <0x20 0x4>;
> > +            #clock-cells = <0>;
> > +            clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
> > +            clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
> > +            clock-output-names = "cmux1";
> > +        };
> > +
> > +        platform-pll@c00 {
> > +            #clock-cells = <1>;
> > +            reg = <0xc00 0x4>;
> > +            compatible = "fsl,qoriq-platform-pll-1.0";
> > +            clocks = <&sysclk>;
> > +            clock-output-names = "platform-pll", "platform-pll-div2";
> > +        };
> > +    };
diff mbox series

Patch

diff --git a/Documentation/devicetree/bindings/clock/fsl,qoriq-clock-legacy.yaml b/Documentation/devicetree/bindings/clock/fsl,qoriq-clock-legacy.yaml
new file mode 100644
index 0000000000000..97b96a1a58254
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/fsl,qoriq-clock-legacy.yaml
@@ -0,0 +1,84 @@ 
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/fsl,qoriq-clock-legacy.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Legacy Clock Block on Freescale QorIQ Platforms
+
+maintainers:
+  - Frank Li <Frank.Li@nxp.com>
+
+description: |
+  These nodes are deprecated.  Kernels should continue to support
+  device trees with these nodes, but new device trees should not use them.
+
+  Most of the bindings are from the common clock binding[1].
+  [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
+
+properties:
+  compatible:
+    enum:
+      - fsl,qoriq-core-pll-1.0
+      - fsl,qoriq-core-pll-2.0
+      - fsl,qoriq-core-mux-1.0
+      - fsl,qoriq-core-mux-2.0
+      - fsl,qoriq-sysclk-1.0
+      - fsl,qoriq-sysclk-2.0
+      - fsl,qoriq-platform-pll-1.0
+      - fsl,qoriq-platform-pll-2.0
+
+  reg:
+    maxItems: 1
+
+  clocks:
+    minItems: 1
+    maxItems: 4
+
+  clock-names:
+    minItems: 1
+    maxItems: 4
+
+  clock-output-names:
+    minItems: 1
+    maxItems: 8
+
+  '#clock-cells':
+    minimum: 0
+    maximum: 1
+
+required:
+  - compatible
+  - '#clock-cells'
+
+additionalProperties: false
+
+allOf:
+  - if:
+      properties:
+        compatible:
+          contains:
+            enum:
+              - fsl,qoriq-sysclk-1.0
+              - fsl,qoriq-sysclk-2.0
+    then:
+      properties:
+        '#clock-cells':
+          const: 0
+
+  - if:
+      properties:
+        compatible:
+          contains:
+            enum:
+              - fsl,qoriq-core-pll-1.0
+              - fsl,qoriq-core-pll-2.0
+    then:
+      properties:
+        '#clock-cells':
+          const: 1
+          description: |
+            * 0 - equal to the PLL frequency
+            * 1 - equal to the PLL frequency divided by 2
+            * 2 - equal to the PLL frequency divided by 4
+
diff --git a/Documentation/devicetree/bindings/clock/fsl,qoriq-clock.yaml b/Documentation/devicetree/bindings/clock/fsl,qoriq-clock.yaml
new file mode 100644
index 0000000000000..d641756b04635
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/fsl,qoriq-clock.yaml
@@ -0,0 +1,203 @@ 
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/fsl,qoriq-clock.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Clock Block on Freescale QorIQ Platforms
+
+maintainers:
+  - Frank Li <Frank.Li@nxp.com>
+
+
+description: |
+
+  Freescale QorIQ chips take primary clocking input from the external
+  SYSCLK signal. The SYSCLK input (frequency) is multiplied using
+  multiple phase locked loops (PLL) to create a variety of frequencies
+  which can then be passed to a variety of internal logic, including
+  cores and peripheral IP blocks.
+  Please refer to the Reference Manual for details.
+
+  All references to "1.0" and "2.0" refer to the QorIQ chassis version to
+  which the chip complies.
+
+  Chassis Version    Example Chips
+  ---------------    -------------
+       1.0      p4080, p5020, p5040
+       2.0      t4240, b4860
+
+  Clock Provider
+
+  The clockgen node should act as a clock provider, though in older device
+  trees the children of the clockgen node are the clock providers.
+
+properties:
+  compatible:
+    items:
+      - enum:
+          - fsl,p2041-clockgen
+          - fsl,p3041-clockgen
+          - fsl,p4080-clockgen
+          - fsl,p5020-clockgen
+          - fsl,p5040-clockgen
+          - fsl,t1023-clockgen
+          - fsl,t1024-clockgen
+          - fsl,t1040-clockgen
+          - fsl,t1042-clockgen
+          - fsl,t2080-clockgen
+          - fsl,t2081-clockgen
+          - fsl,t4240-clockgen
+          - fsl,b4420-clockgen
+          - fsl,b4860-clockgen
+          - fsl,ls1012a-clockgen
+          - fsl,ls1021a-clockgen
+          - fsl,ls1028a-clockgen
+          - fsl,ls1043a-clockgen
+          - fsl,ls1046a-clockgen
+          - fsl,ls1088a-clockgen
+          - fsl,ls2080a-clockgen
+          - fsl,lx2160a-clockgen
+      - enum:
+          - fsl,qoriq-clockgen-1.0
+          - fsl,qoriq-clockgen-2.0
+    minItems: 1
+
+  reg:
+    maxItems: 1
+
+  ranges: true
+
+  '#address-cells':
+    const: 1
+
+  '#size-cells':
+    const: 1
+
+  '#clock-cells':
+    const: 2
+    description: |
+      The first cell of the clock specifier is the clock type, and the
+      second cell is the clock index for the specified type.
+
+        Type#  Name       Index Cell
+        0  sysclk          must be 0
+        1  cmux            index (n in CLKCnCSR)
+        2  hwaccel         index (n in CLKCGnHWACSR)
+        3  fman            0 for fm1, 1 for fm2
+        4  platform pll    n=pll/(n+1). For example, when n=1,
+                          that means output_freq=PLL_freq/2.
+        5  coreclk         must be 0
+
+  clock-frequency:
+    description: Input system clock frequency (SYSCLK)
+
+  clocks:
+    items:
+      - description:
+          sysclk may be provided as an input clock.  Either clock-frequency
+          or clocks must be provided.
+      - description:
+          A second input clock, called "coreclk", may be provided if
+          core PLLs are based on a different input clock from the
+          platform PLL.
+    minItems: 1
+
+  clock-names:
+    items:
+      - const: sysclk
+      - const: coreclk
+
+patternProperties:
+  '^mux[0-9]@[a-f0-9]+$':
+    deprecated: true
+    $ref: fsl,qoriq-clock-legacy.yaml
+
+  '^sysclk+$':
+    deprecated: true
+    $ref: fsl,qoriq-clock-legacy.yaml
+
+  '^pll[0-9]@[a-f0-9]+$':
+    deprecated: true
+    $ref: fsl,qoriq-clock-legacy.yaml
+
+  '^platform\-pll@[a-f0-9]+$':
+    deprecated: true
+    $ref: fsl,qoriq-clock-legacy.yaml
+
+required:
+  - compatible
+  - reg
+  - '#clock-cells'
+
+additionalProperties: false
+
+examples:
+  - |
+    /* clock provider example */
+    global-utilities@e1000 {
+        compatible = "fsl,p5020-clockgen", "fsl,qoriq-clockgen-1.0";
+        reg = <0xe1000 0x1000>;
+        clock-frequency = <133333333>;
+        #clock-cells = <2>;
+    };
+
+  - |
+    /* Legacy example */
+    global-utilities@e1000 {
+        compatible = "fsl,p5020-clockgen", "fsl,qoriq-clockgen-1.0";
+        reg = <0xe1000 0x1000>;
+        ranges = <0x0 0xe1000 0x1000>;
+        clock-frequency = <133333333>;
+        #address-cells = <1>;
+        #size-cells = <1>;
+        #clock-cells = <2>;
+
+        sysclk: sysclk {
+            compatible = "fsl,qoriq-sysclk-1.0";
+            clock-output-names = "sysclk";
+            #clock-cells = <0>;
+        };
+
+        pll0: pll0@800 {
+            compatible = "fsl,qoriq-core-pll-1.0";
+            reg = <0x800 0x4>;
+            #clock-cells = <1>;
+            clocks = <&sysclk>;
+            clock-output-names = "pll0", "pll0-div2";
+        };
+
+        pll1: pll1@820 {
+            compatible = "fsl,qoriq-core-pll-1.0";
+            reg = <0x820 0x4>;
+            #clock-cells = <1>;
+            clocks = <&sysclk>;
+            clock-output-names = "pll1", "pll1-div2";
+        };
+
+        mux0: mux0@0 {
+            compatible = "fsl,qoriq-core-mux-1.0";
+            reg = <0x0 0x4>;
+            #clock-cells = <0>;
+            clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
+            clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
+            clock-output-names = "cmux0";
+        };
+
+        mux1: mux1@20 {
+            compatible = "fsl,qoriq-core-mux-1.0";
+            reg = <0x20 0x4>;
+            #clock-cells = <0>;
+            clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
+            clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
+            clock-output-names = "cmux1";
+        };
+
+        platform-pll@c00 {
+            #clock-cells = <1>;
+            reg = <0xc00 0x4>;
+            compatible = "fsl,qoriq-platform-pll-1.0";
+            clocks = <&sysclk>;
+            clock-output-names = "platform-pll", "platform-pll-div2";
+        };
+    };
diff --git a/Documentation/devicetree/bindings/clock/qoriq-clock.txt b/Documentation/devicetree/bindings/clock/qoriq-clock.txt
deleted file mode 100644
index 10119d9ef4b11..0000000000000
--- a/Documentation/devicetree/bindings/clock/qoriq-clock.txt
+++ /dev/null
@@ -1,212 +0,0 @@ 
-* Clock Block on Freescale QorIQ Platforms
-
-Freescale QorIQ chips take primary clocking input from the external
-SYSCLK signal. The SYSCLK input (frequency) is multiplied using
-multiple phase locked loops (PLL) to create a variety of frequencies
-which can then be passed to a variety of internal logic, including
-cores and peripheral IP blocks.
-Please refer to the Reference Manual for details.
-
-All references to "1.0" and "2.0" refer to the QorIQ chassis version to
-which the chip complies.
-
-Chassis Version		Example Chips
----------------		-------------
-1.0			p4080, p5020, p5040
-2.0			t4240, b4860
-
-1. Clock Block Binding
-
-Required properties:
-- compatible: Should contain a chip-specific clock block compatible
-	string and (if applicable) may contain a chassis-version clock
-	compatible string.
-
-	Chip-specific strings are of the form "fsl,<chip>-clockgen", such as:
-	* "fsl,p2041-clockgen"
-	* "fsl,p3041-clockgen"
-	* "fsl,p4080-clockgen"
-	* "fsl,p5020-clockgen"
-	* "fsl,p5040-clockgen"
-	* "fsl,t1023-clockgen"
-	* "fsl,t1024-clockgen"
-	* "fsl,t1040-clockgen"
-	* "fsl,t1042-clockgen"
-	* "fsl,t2080-clockgen"
-	* "fsl,t2081-clockgen"
-	* "fsl,t4240-clockgen"
-	* "fsl,b4420-clockgen"
-	* "fsl,b4860-clockgen"
-	* "fsl,ls1012a-clockgen"
-	* "fsl,ls1021a-clockgen"
-	* "fsl,ls1028a-clockgen"
-	* "fsl,ls1043a-clockgen"
-	* "fsl,ls1046a-clockgen"
-	* "fsl,ls1088a-clockgen"
-	* "fsl,ls2080a-clockgen"
-	* "fsl,lx2160a-clockgen"
-	Chassis-version clock strings include:
-	* "fsl,qoriq-clockgen-1.0": for chassis 1.0 clocks
-	* "fsl,qoriq-clockgen-2.0": for chassis 2.0 clocks
-- reg: Describes the address of the device's resources within the
-	address space defined by its parent bus, and resource zero
-	represents the clock register set
-
-Optional properties:
-- ranges: Allows valid translation between child's address space and
-	parent's. Must be present if the device has sub-nodes.
-- #address-cells: Specifies the number of cells used to represent
-	physical base addresses.  Must be present if the device has
-	sub-nodes and set to 1 if present
-- #size-cells: Specifies the number of cells used to represent
-	the size of an address. Must be present if the device has
-	sub-nodes and set to 1 if present
-- clock-frequency: Input system clock frequency (SYSCLK)
-- clocks: If clock-frequency is not specified, sysclk may be provided
-	as an input clock.  Either clock-frequency or clocks must be
-	provided.
-	A second input clock, called "coreclk", may be provided if
-	core PLLs are based on a different input clock from the
-	platform PLL.
-- clock-names: Required if a coreclk is present.  Valid names are
-	"sysclk" and "coreclk".
-
-2. Clock Provider
-
-The clockgen node should act as a clock provider, though in older device
-trees the children of the clockgen node are the clock providers.
-
-When the clockgen node is a clock provider, #clock-cells = <2>.
-The first cell of the clock specifier is the clock type, and the
-second cell is the clock index for the specified type.
-
-	Type#	Name		Index Cell
-	0	sysclk		must be 0
-	1	cmux		index (n in CLKCnCSR)
-	2	hwaccel		index (n in CLKCGnHWACSR)
-	3	fman		0 for fm1, 1 for fm2
-	4	platform pll	n=pll/(n+1). For example, when n=1,
-				that means output_freq=PLL_freq/2.
-	5	coreclk		must be 0
-
-3. Example
-
-	clockgen: global-utilities@e1000 {
-		compatible = "fsl,p5020-clockgen", "fsl,qoriq-clockgen-1.0";
-		clock-frequency = <133333333>;
-		reg = <0xe1000 0x1000>;
-		#clock-cells = <2>;
-	};
-
-	fman@400000 {
-		...
-		clocks = <&clockgen 3 0>;
-		...
-	};
-}
-4. Legacy Child Nodes
-
-NOTE: These nodes are deprecated.  Kernels should continue to support
-device trees with these nodes, but new device trees should not use them.
-
-Most of the bindings are from the common clock binding[1].
- [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
-
-Required properties:
-- compatible : Should include one of the following:
-	* "fsl,qoriq-core-pll-1.0" for core PLL clocks (v1.0)
-	* "fsl,qoriq-core-pll-2.0" for core PLL clocks (v2.0)
-	* "fsl,qoriq-core-mux-1.0" for core mux clocks (v1.0)
-	* "fsl,qoriq-core-mux-2.0" for core mux clocks (v2.0)
-	* "fsl,qoriq-sysclk-1.0": for input system clock (v1.0).
-		It takes parent's clock-frequency as its clock.
-	* "fsl,qoriq-sysclk-2.0": for input system clock (v2.0).
-		It takes parent's clock-frequency as its clock.
-	* "fsl,qoriq-platform-pll-1.0" for the platform PLL clock (v1.0)
-	* "fsl,qoriq-platform-pll-2.0" for the platform PLL clock (v2.0)
-- #clock-cells: From common clock binding. The number of cells in a
-	clock-specifier. Should be <0> for "fsl,qoriq-sysclk-[1,2].0"
-	clocks, or <1> for "fsl,qoriq-core-pll-[1,2].0" clocks.
-	For "fsl,qoriq-core-pll-[1,2].0" clocks, the single
-	clock-specifier cell may take the following values:
-	* 0 - equal to the PLL frequency
-	* 1 - equal to the PLL frequency divided by 2
-	* 2 - equal to the PLL frequency divided by 4
-
-Recommended properties:
-- clocks: Should be the phandle of input parent clock
-- clock-names: From common clock binding, indicates the clock name
-- clock-output-names: From common clock binding, indicates the names of
-	output clocks
-- reg: Should be the offset and length of clock block base address.
-	The length should be 4.
-
-Legacy Example:
-/ {
-	clockgen: global-utilities@e1000 {
-		compatible = "fsl,p5020-clockgen", "fsl,qoriq-clockgen-1.0";
-		ranges = <0x0 0xe1000 0x1000>;
-		clock-frequency = <133333333>;
-		reg = <0xe1000 0x1000>;
-		#address-cells = <1>;
-		#size-cells = <1>;
-
-		sysclk: sysclk {
-			#clock-cells = <0>;
-			compatible = "fsl,qoriq-sysclk-1.0";
-			clock-output-names = "sysclk";
-		};
-
-		pll0: pll0@800 {
-			#clock-cells = <1>;
-			reg = <0x800 0x4>;
-			compatible = "fsl,qoriq-core-pll-1.0";
-			clocks = <&sysclk>;
-			clock-output-names = "pll0", "pll0-div2";
-		};
-
-		pll1: pll1@820 {
-			#clock-cells = <1>;
-			reg = <0x820 0x4>;
-			compatible = "fsl,qoriq-core-pll-1.0";
-			clocks = <&sysclk>;
-			clock-output-names = "pll1", "pll1-div2";
-		};
-
-		mux0: mux0@0 {
-			#clock-cells = <0>;
-			reg = <0x0 0x4>;
-			compatible = "fsl,qoriq-core-mux-1.0";
-			clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
-			clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
-			clock-output-names = "cmux0";
-		};
-
-		mux1: mux1@20 {
-			#clock-cells = <0>;
-			reg = <0x20 0x4>;
-			compatible = "fsl,qoriq-core-mux-1.0";
-			clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
-			clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
-			clock-output-names = "cmux1";
-		};
-
-		platform-pll: platform-pll@c00 {
-			#clock-cells = <1>;
-			reg = <0xc00 0x4>;
-			compatible = "fsl,qoriq-platform-pll-1.0";
-			clocks = <&sysclk>;
-			clock-output-names = "platform-pll", "platform-pll-div2";
-		};
-	};
-};
-
-Example for legacy clock consumer:
-
-/ {
-	cpu0: PowerPC,e5500@0 {
-		...
-		clocks = <&mux0>;
-		...
-	};
-};