diff mbox series

arm64: dts: freescale: imx8mp-phyboard-pollux-rdk: add HDMI support

Message ID 20240716083635.626596-1-cwecht@mailbox.org (mailing list archive)
State New
Headers show
Series arm64: dts: freescale: imx8mp-phyboard-pollux-rdk: add HDMI support | expand

Commit Message

Christopher Wecht July 16, 2024, 8:36 a.m. UTC
Enable the HDMI output on the phyBOARD Pollux, using the HDMI encoder
present in the i.MX8MP SoC.

Please note that lcdif3 has not bee enabled. This is due the fact
that as of now either HDMI or LVDS may be enabled. If both are
enabled it won't worked. With this patch, however, HDMI can be
enabled by turning ldcif3 on and ldcif2 off.

Signed-off-by: Christopher Wecht <cwecht@mailbox.org>
---
 .../freescale/imx8mp-phyboard-pollux-rdk.dts  | 53 +++++++++++++++++++
 1 file changed, 53 insertions(+)

Comments

Rob Herring (Arm) July 16, 2024, 9:12 p.m. UTC | #1
On Tue, 16 Jul 2024 10:36:35 +0200, Christopher Wecht wrote:
> Enable the HDMI output on the phyBOARD Pollux, using the HDMI encoder
> present in the i.MX8MP SoC.
> 
> Please note that lcdif3 has not bee enabled. This is due the fact
> that as of now either HDMI or LVDS may be enabled. If both are
> enabled it won't worked. With this patch, however, HDMI can be
> enabled by turning ldcif3 on and ldcif2 off.
> 
> Signed-off-by: Christopher Wecht <cwecht@mailbox.org>
> ---
>  .../freescale/imx8mp-phyboard-pollux-rdk.dts  | 53 +++++++++++++++++++
>  1 file changed, 53 insertions(+)
> 


My bot found new DTB warnings on the .dts files added or changed in this
series.

Some warnings may be from an existing SoC .dtsi. Or perhaps the warnings
are fixed by another series. Ultimately, it is up to the platform
maintainer whether these warnings are acceptable or not. No need to reply
unless the platform maintainer has comments.

If you already ran DT checks and didn't see these error(s), then
make sure dt-schema is up to date:

  pip3 install dtschema --upgrade


New warnings running 'make CHECK_DTBS=y freescale/imx8mp-phyboard-pollux-rdk.dtb' for 20240716083635.626596-1-cwecht@mailbox.org:

Error: arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dts:149.17-153.12 syntax error
FATAL ERROR: Unable to parse input tree
make[3]: *** [scripts/Makefile.lib:442: arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dtb] Error 1
make[2]: *** [scripts/Makefile.build:485: arch/arm64/boot/dts/freescale] Error 2
make[2]: Target 'arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dtb' not remade because of errors.
make[1]: *** [/home/rob/proj/linux-dt-testing/Makefile:1381: freescale/imx8mp-phyboard-pollux-rdk.dtb] Error 2
make: *** [Makefile:224: __sub-make] Error 2
make: Target 'freescale/imx8mp-phyboard-pollux-rdk.dtb' not remade because of errors.
diff mbox series

Patch

diff --git a/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dts b/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dts
index 00a240484c25..3ea67bada2c1 100644
--- a/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dts
@@ -101,6 +101,18 @@  reg_vcc_3v3_sw: regulator-vcc-3v3-sw {
 		regulator-min-microvolt = <3300000>;
 		regulator-max-microvolt = <3300000>;
 	};
+
+	hdmi-connector {
+		compatible = "hdmi-connector";
+		label = "hdmi";
+		type = "a";
+
+		port {
+			hdmi_connector_in: endpoint {
+				remote-endpoint = <&hdmi_tx_out>;
+			};
+		};
+	};
 };
 
 &eqos {
@@ -127,6 +139,38 @@  ethphy0: ethernet-phy@1 {
 	};
 };
 
+
+/* HDMI */
+&irqsteer_hdmi {
+	status = "okay";
+};
+
+&hdmi_blk_ctrl {
+	status = "okay"";
+};
+
+&hdmi_pvi {
+	status = "okay"";
+};
+
+&hdmi_tx {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_hdmi>;
+	status = "okay"";
+
+	ports {
+		port@1 {
+			hdmi_tx_out: endpoint {
+				remote-endpoint = <&hdmi_connector_in>;
+			};
+		};
+	};
+};
+
+&hdmi_tx_phy {
+	status = "okay";
+};
+
 /* CAN FD */
 &flexcan1 {
 	pinctrl-names = "default";
@@ -346,6 +390,15 @@  MX8MP_IOMUXC_SAI5_RXD0__GPIO3_IO21	0x154
 		>;
 	};
 
+	pinctrl_hdmi: hdmigrp {
+		fsl,pins = <
+			MX8MP_IOMUXC_HDMI_DDC_SCL__HDMIMIX_HDMI_SCL     0x400001c3
+			MX8MP_IOMUXC_HDMI_DDC_SDA__HDMIMIX_HDMI_SDA     0x400001c3
+			MX8MP_IOMUXC_HDMI_HPD__HDMIMIX_HDMI_HPD         0x40000019
+			MX8MP_IOMUXC_HDMI_CEC__HDMIMIX_HDMI_CEC         0x40000019
+		>;
+	};
+
 	pinctrl_i2c2: i2c2grp {
 		fsl,pins = <
 			MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL		0x400001c2