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[34.90.227.64]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-5bbb2c29f79sm671761a12.33.2024.08.08.07.11.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 08 Aug 2024 07:11:22 -0700 (PDT) From: =?utf-8?q?Andr=C3=A9_Draszik?= Date: Thu, 08 Aug 2024 15:11:27 +0100 Subject: [PATCH v5 13/20] clk: imx: imx7ulp: drop calls to imx_register_uart_clocks() Precedence: bulk X-Mailing-List: imx@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240808-gs101-non-essential-clocks-2-v5-13-11cffef0634e@linaro.org> References: <20240808-gs101-non-essential-clocks-2-v5-0-11cffef0634e@linaro.org> In-Reply-To: <20240808-gs101-non-essential-clocks-2-v5-0-11cffef0634e@linaro.org> To: Michael Turquette , Stephen Boyd , Peter Griffin , Krzysztof Kozlowski , Sylwester Nawrocki , Chanwoo Choi , Alim Akhtar , Sam Protsenko , Tudor Ambarus , Abel Vesa , Peng Fan , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam Cc: Will McVicker , kernel-team@android.com, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, imx@lists.linux.dev, =?utf-8?q?Andr=C3=A9_Draszik?= X-Mailer: b4 0.13.0 The clk core now does something similar for us as part of of_clk_add_provider() and of_clk_add_hw_provider() and this i.MX specific call isn't necessary anymore. This should also plug a memory and clock reference leak due to multiple calls to imx_register_uart_clocks(), one for each clock unit. Signed-off-by: André Draszik --- drivers/clk/imx/clk-imx7ulp.c | 4 ---- 1 file changed, 4 deletions(-) diff --git a/drivers/clk/imx/clk-imx7ulp.c b/drivers/clk/imx/clk-imx7ulp.c index f4a48a42637f..517fb388ce85 100644 --- a/drivers/clk/imx/clk-imx7ulp.c +++ b/drivers/clk/imx/clk-imx7ulp.c @@ -175,8 +175,6 @@ static void __init imx7ulp_clk_pcc2_init(struct device_node *np) imx_check_clk_hws(hws, clk_data->num); of_clk_add_hw_provider(np, of_clk_hw_onecell_get, clk_data); - - imx_register_uart_clocks(); } CLK_OF_DECLARE(imx7ulp_clk_pcc2, "fsl,imx7ulp-pcc2", imx7ulp_clk_pcc2_init); @@ -222,8 +220,6 @@ static void __init imx7ulp_clk_pcc3_init(struct device_node *np) imx_check_clk_hws(hws, clk_data->num); of_clk_add_hw_provider(np, of_clk_hw_onecell_get, clk_data); - - imx_register_uart_clocks(); } CLK_OF_DECLARE(imx7ulp_clk_pcc3, "fsl,imx7ulp-pcc3", imx7ulp_clk_pcc3_init);