| Message ID | 20240813-wip-bhahn-add_pcie_support-v1-1-c1bb062b4e1f@phytec.de (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | arm64: dts: imx8mp-phyboard-pollux-rdk: Add support for PCIe | expand |
Hello Benjamin, On Tue, 2024-08-13 at 14:02 +0200, Benjamin Hahn wrote: > Add support for the Mini PCIe slot. > > Signed-off-by: Benjamin Hahn <B.Hahn@phytec.de> > --- > .../dts/freescale/imx8mp-phyboard-pollux-rdk.dts | 42 ++++++++++++++++++++++ > 1 file changed, 42 insertions(+) > > diff --git a/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dts > b/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dts > index 00a240484c25..0ecb2f62c37f 100644 > --- a/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dts > +++ b/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dts > @@ -6,6 +6,7 @@ > > /dts-v1/; > > +#include <dt-bindings/phy/phy-imx8-pcie.h> > #include <dt-bindings/leds/leds-pca9532.h> > #include <dt-bindings/pwm/pwm.h> > #include "imx8mp-phycore-som.dtsi" > @@ -63,6 +64,17 @@ reg_can2_stby: regulator-can2-stby { > regulator-name = "can2-stby"; > }; > > + reg_pcie0: regulator-pcie { > + compatible = "regulator-fixed"; > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_pcie0_reg>; > + regulator-name = "MPCIE_3V3"; > + regulator-min-microvolt = <3300000>; > + regulator-max-microvolt = <3300000>; > + gpio = <&gpio1 14 GPIO_ACTIVE_HIGH>; > + enable-active-high; > + }; > + pcie uses the reg_vcc_3v3_sw. Drop this node and use the appropriate regulator instead. > reg_lvds1_reg_en: regulator-lvds1 { > compatible = "regulator-fixed"; > enable-active-high; > @@ -195,6 +207,23 @@ &snvs_pwrkey { > status = "okay"; > }; > > +&pcie_phy { > + fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_OUTPUT>; > + fsl,clkreq-unsupported; Why do you have this as unsupported? We have a GPIO connected to CLKREQ. > + clocks = <&hsio_blk_ctrl>; > + clock-names = "ref"; > + status = "okay"; > +}; > + > +/* Mini PCIe */ > +&pcie { > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_pcie0>; > + reset-gpio = <&gpio1 8 GPIO_ACTIVE_LOW>; > + vpcie-supply = <®_pcie0>; > + status = "okay"; > +}; > + > &pwm3 { > status = "okay"; > pinctrl-names = "default"; > @@ -366,6 +395,19 @@ MX8MP_IOMUXC_SD2_WP__GPIO2_IO20 0x12 > >; > }; > > + pinctrl_pcie0: pcie0grp { > + fsl,pins = < > + MX8MP_IOMUXC_GPIO1_IO11__GPIO1_IO11 0x60 /* open drain, pull up */ > + MX8MP_IOMUXC_GPIO1_IO08__GPIO1_IO08 0x40 Can you please reorder numerically ascending? You are missing GPIO1 10 used for WAKE#. > + >; > + }; > + > + pinctrl_pcie0_reg: pcie0reggrp { > + fsl,pins = < > + MX8MP_IOMUXC_GPIO1_IO14__GPIO1_IO14 0x40 This gpio muxing should be in the pcie0grp. Yannic > + >; > + }; > + > pinctrl_pwm3: pwm3grp { > fsl,pins = < > MX8MP_IOMUXC_SPDIF_TX__PWM3_OUT 0x12 > > --- > base-commit: 7c626ce4bae1ac14f60076d00eafe71af30450ba > change-id: 20240813-wip-bhahn-add_pcie_support-b9bd75fc4d98 > > Best regards,
Hi Yannic, On 20.08.24 10:52, Yannic Moog wrote: > Hello Benjamin, > > On Tue, 2024-08-13 at 14:02 +0200, Benjamin Hahn wrote: >> Add support for the Mini PCIe slot. >> >> Signed-off-by: Benjamin Hahn <B.Hahn@phytec.de> >> --- >> .../dts/freescale/imx8mp-phyboard-pollux-rdk.dts | 42 ++++++++++++++++++++++ >> 1 file changed, 42 insertions(+) >> >> diff --git a/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dts >> b/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dts >> index 00a240484c25..0ecb2f62c37f 100644 >> --- a/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dts >> +++ b/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dts >> @@ -6,6 +6,7 @@ >> >> /dts-v1/; >> >> +#include <dt-bindings/phy/phy-imx8-pcie.h> >> #include <dt-bindings/leds/leds-pca9532.h> >> #include <dt-bindings/pwm/pwm.h> >> #include "imx8mp-phycore-som.dtsi" >> @@ -63,6 +64,17 @@ reg_can2_stby: regulator-can2-stby { >> regulator-name = "can2-stby"; >> }; >> >> + reg_pcie0: regulator-pcie { >> + compatible = "regulator-fixed"; >> + pinctrl-names = "default"; >> + pinctrl-0 = <&pinctrl_pcie0_reg>; >> + regulator-name = "MPCIE_3V3"; >> + regulator-min-microvolt = <3300000>; >> + regulator-max-microvolt = <3300000>; >> + gpio = <&gpio1 14 GPIO_ACTIVE_HIGH>; >> + enable-active-high; >> + }; >> + > pcie uses the reg_vcc_3v3_sw. Drop this node and use the appropriate regulator instead. ok > >> reg_lvds1_reg_en: regulator-lvds1 { >> compatible = "regulator-fixed"; >> enable-active-high; >> @@ -195,6 +207,23 @@ &snvs_pwrkey { >> status = "okay"; >> }; >> >> +&pcie_phy { >> + fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_OUTPUT>; >> + fsl,clkreq-unsupported; > Why do you have this as unsupported? We have a GPIO connected to CLKREQ. It looks like the pcie driver does not support using a GPIO for clkreq. So it does not work for us. > >> + clocks = <&hsio_blk_ctrl>; >> + clock-names = "ref"; >> + status = "okay"; >> +}; >> + >> +/* Mini PCIe */ >> +&pcie { >> + pinctrl-names = "default"; >> + pinctrl-0 = <&pinctrl_pcie0>; >> + reset-gpio = <&gpio1 8 GPIO_ACTIVE_LOW>; >> + vpcie-supply = <®_pcie0>; >> + status = "okay"; >> +}; >> + >> &pwm3 { >> status = "okay"; >> pinctrl-names = "default"; >> @@ -366,6 +395,19 @@ MX8MP_IOMUXC_SD2_WP__GPIO2_IO20 0x12 >> >; >> }; >> >> + pinctrl_pcie0: pcie0grp { >> + fsl,pins = < >> + MX8MP_IOMUXC_GPIO1_IO11__GPIO1_IO11 0x60 /* open drain, pull up */ >> + MX8MP_IOMUXC_GPIO1_IO08__GPIO1_IO08 0x40 > Can you please reorder numerically ascending? > You are missing GPIO1 10 used for WAKE#. ok Benjamin > >> + >; >> + }; >> + >> + pinctrl_pcie0_reg: pcie0reggrp { >> + fsl,pins = < >> + MX8MP_IOMUXC_GPIO1_IO14__GPIO1_IO14 0x40 > This gpio muxing should be in the pcie0grp. > > Yannic > >> + >; >> + }; >> + >> pinctrl_pwm3: pwm3grp { >> fsl,pins = < >> MX8MP_IOMUXC_SPDIF_TX__PWM3_OUT 0x12 >> >> --- >> base-commit: 7c626ce4bae1ac14f60076d00eafe71af30450ba >> change-id: 20240813-wip-bhahn-add_pcie_support-b9bd75fc4d98 >> >> Best regards,
diff --git a/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dts b/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dts index 00a240484c25..0ecb2f62c37f 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dts @@ -6,6 +6,7 @@ /dts-v1/; +#include <dt-bindings/phy/phy-imx8-pcie.h> #include <dt-bindings/leds/leds-pca9532.h> #include <dt-bindings/pwm/pwm.h> #include "imx8mp-phycore-som.dtsi" @@ -63,6 +64,17 @@ reg_can2_stby: regulator-can2-stby { regulator-name = "can2-stby"; }; + reg_pcie0: regulator-pcie { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie0_reg>; + regulator-name = "MPCIE_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio1 14 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + reg_lvds1_reg_en: regulator-lvds1 { compatible = "regulator-fixed"; enable-active-high; @@ -195,6 +207,23 @@ &snvs_pwrkey { status = "okay"; }; +&pcie_phy { + fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_OUTPUT>; + fsl,clkreq-unsupported; + clocks = <&hsio_blk_ctrl>; + clock-names = "ref"; + status = "okay"; +}; + +/* Mini PCIe */ +&pcie { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie0>; + reset-gpio = <&gpio1 8 GPIO_ACTIVE_LOW>; + vpcie-supply = <®_pcie0>; + status = "okay"; +}; + &pwm3 { status = "okay"; pinctrl-names = "default"; @@ -366,6 +395,19 @@ MX8MP_IOMUXC_SD2_WP__GPIO2_IO20 0x12 >; }; + pinctrl_pcie0: pcie0grp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO11__GPIO1_IO11 0x60 /* open drain, pull up */ + MX8MP_IOMUXC_GPIO1_IO08__GPIO1_IO08 0x40 + >; + }; + + pinctrl_pcie0_reg: pcie0reggrp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO14__GPIO1_IO14 0x40 + >; + }; + pinctrl_pwm3: pwm3grp { fsl,pins = < MX8MP_IOMUXC_SPDIF_TX__PWM3_OUT 0x12
Add support for the Mini PCIe slot. Signed-off-by: Benjamin Hahn <B.Hahn@phytec.de> --- .../dts/freescale/imx8mp-phyboard-pollux-rdk.dts | 42 ++++++++++++++++++++++ 1 file changed, 42 insertions(+) --- base-commit: 7c626ce4bae1ac14f60076d00eafe71af30450ba change-id: 20240813-wip-bhahn-add_pcie_support-b9bd75fc4d98 Best regards,