diff mbox series

[v3] arm64: dts: imx8mp: Add DT nodes for the two ISPs

Message ID 20240813234004.17807-1-laurent.pinchart@ideasonboard.com (mailing list archive)
State Superseded
Headers show
Series [v3] arm64: dts: imx8mp: Add DT nodes for the two ISPs | expand

Commit Message

Laurent Pinchart Aug. 13, 2024, 11:40 p.m. UTC
From: Paul Elder <paul.elder@ideasonboard.com>

The ISP supports both CSI and parallel interfaces, where port 0
corresponds to the former and port 1 corresponds to the latter. Since
the i.MX8MP's ISPs are connected by the parallel interface to the CSI
receiver, set them both to port 1.

Signed-off-by: Paul Elder <paul.elder@ideasonboard.com>
Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Tested-by: Adam Ford <aford173@gmail.com> # imx8mp-beacon
---
Changes since v2:

- Assign clock parent and frequency in blk-ctrl

Changes since v1:

- Fix clock ordering
- Add #address-cells and #size-cells to ports nodes
---
 arch/arm64/boot/dts/freescale/imx8mp.dtsi | 51 ++++++++++++++++++++++-
 1 file changed, 49 insertions(+), 2 deletions(-)


base-commit: 7c626ce4bae1ac14f60076d00eafe71af30450ba

Comments

Alexander Stein Aug. 14, 2024, 10:02 a.m. UTC | #1
Hi Laurent,

thanks for the patch.

Am Mittwoch, 14. August 2024, 01:40:04 CEST schrieb Laurent Pinchart:
> From: Paul Elder <paul.elder@ideasonboard.com>
> 
> The ISP supports both CSI and parallel interfaces, where port 0
> corresponds to the former and port 1 corresponds to the latter. Since
> the i.MX8MP's ISPs are connected by the parallel interface to the CSI
> receiver, set them both to port 1.
> 
> Signed-off-by: Paul Elder <paul.elder@ideasonboard.com>
> Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
> Tested-by: Adam Ford <aford173@gmail.com> # imx8mp-beacon
> ---
> Changes since v2:
> 
> - Assign clock parent and frequency in blk-ctrl
> 
> Changes since v1:
> 
> - Fix clock ordering
> - Add #address-cells and #size-cells to ports nodes
> ---
>  arch/arm64/boot/dts/freescale/imx8mp.dtsi | 51 ++++++++++++++++++++++-
>  1 file changed, 49 insertions(+), 2 deletions(-)
> 
> diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
> index d9b5c40f6460..09f1e27ee220 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
> @@ -1673,6 +1673,50 @@ isi_in_1: endpoint {
>  				};
>  			};
>  
> +			isp_0: isp@32e10000 {
> +				compatible = "fsl,imx8mp-isp";
> +				reg = <0x32e10000 0x10000>;
> +				interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
> +				clocks = <&clk IMX8MP_CLK_MEDIA_ISP_ROOT>,
> +					 <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>,
> +					 <&clk IMX8MP_CLK_MEDIA_APB_ROOT>;
> +				clock-names = "isp", "aclk", "hclk";
> +				power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_ISP>;
> +				fsl,blk-ctrl = <&media_blk_ctrl 0>;
> +				status = "disabled";
> +
> +				ports {
> +					#address-cells = <1>;
> +					#size-cells = <0>;
> +
> +					port@1 {
> +						reg = <1>;
> +					};
> +				};
> +			};
> +
> +			isp_1: isp@32e20000 {
> +				compatible = "fsl,imx8mp-isp";
> +				reg = <0x32e20000 0x10000>;
> +				interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
> +				clocks = <&clk IMX8MP_CLK_MEDIA_ISP_ROOT>,
> +					 <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>,
> +					 <&clk IMX8MP_CLK_MEDIA_APB_ROOT>;
> +				clock-names = "isp", "aclk", "hclk";
> +				power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_ISP>;
> +				fsl,blk-ctrl = <&media_blk_ctrl 1>;
> +				status = "disabled";
> +
> +				ports {
> +					#address-cells = <1>;
> +					#size-cells = <0>;
> +
> +					port@1 {
> +						reg = <1>;
> +					};
> +				};
> +			};
> +
>  			dewarp: dwe@32e30000 {
>  				compatible = "nxp,imx8mp-dw100";
>  				reg = <0x32e30000 0x10000>;
> @@ -1873,13 +1917,16 @@ media_blk_ctrl: blk-ctrl@32ec0000 {
>  						  <&clk IMX8MP_CLK_MEDIA_APB>,
>  						  <&clk IMX8MP_CLK_MEDIA_DISP1_PIX>,
>  						  <&clk IMX8MP_CLK_MEDIA_DISP2_PIX>,
> +						  <&clk IMX8MP_CLK_MEDIA_ISP>,
>  						  <&clk IMX8MP_VIDEO_PLL1>;
>  				assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>,
>  							 <&clk IMX8MP_SYS_PLL1_800M>,
>  							 <&clk IMX8MP_VIDEO_PLL1_OUT>,
> -							 <&clk IMX8MP_VIDEO_PLL1_OUT>;
> +							 <&clk IMX8MP_VIDEO_PLL1_OUT>,
> +							 <&clk IMX8MP_SYS_PLL2_500M>;
>  				assigned-clock-rates = <500000000>, <200000000>,
> -						       <0>, <0>, <1039500000>;
> +						       <0>, <0>, <0>, <500000000>,
> +						       <1039500000>;

Isn't this one '<0>' too much? <500000000> is for IMX8MP_CLK_MEDIA_ISP, right?

Best regards,
Alexander

>  				#power-domain-cells = <1>;
>  
>  				lvds_bridge: bridge@5c {
> 
> base-commit: 7c626ce4bae1ac14f60076d00eafe71af30450ba
>
Laurent Pinchart Aug. 14, 2024, 2:52 p.m. UTC | #2
Hi Alexander,

On Wed, Aug 14, 2024 at 12:02:26PM +0200, Alexander Stein wrote:
> Am Mittwoch, 14. August 2024, 01:40:04 CEST schrieb Laurent Pinchart:
> > From: Paul Elder <paul.elder@ideasonboard.com>
> > 
> > The ISP supports both CSI and parallel interfaces, where port 0
> > corresponds to the former and port 1 corresponds to the latter. Since
> > the i.MX8MP's ISPs are connected by the parallel interface to the CSI
> > receiver, set them both to port 1.
> > 
> > Signed-off-by: Paul Elder <paul.elder@ideasonboard.com>
> > Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
> > Tested-by: Adam Ford <aford173@gmail.com> # imx8mp-beacon
> > ---
> > Changes since v2:
> > 
> > - Assign clock parent and frequency in blk-ctrl
> > 
> > Changes since v1:
> > 
> > - Fix clock ordering
> > - Add #address-cells and #size-cells to ports nodes
> > ---
> >  arch/arm64/boot/dts/freescale/imx8mp.dtsi | 51 ++++++++++++++++++++++-
> >  1 file changed, 49 insertions(+), 2 deletions(-)
> > 
> > diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
> > index d9b5c40f6460..09f1e27ee220 100644
> > --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi
> > +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
> > @@ -1673,6 +1673,50 @@ isi_in_1: endpoint {
> >  				};
> >  			};
> >  
> > +			isp_0: isp@32e10000 {
> > +				compatible = "fsl,imx8mp-isp";
> > +				reg = <0x32e10000 0x10000>;
> > +				interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
> > +				clocks = <&clk IMX8MP_CLK_MEDIA_ISP_ROOT>,
> > +					 <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>,
> > +					 <&clk IMX8MP_CLK_MEDIA_APB_ROOT>;
> > +				clock-names = "isp", "aclk", "hclk";
> > +				power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_ISP>;
> > +				fsl,blk-ctrl = <&media_blk_ctrl 0>;
> > +				status = "disabled";
> > +
> > +				ports {
> > +					#address-cells = <1>;
> > +					#size-cells = <0>;
> > +
> > +					port@1 {
> > +						reg = <1>;
> > +					};
> > +				};
> > +			};
> > +
> > +			isp_1: isp@32e20000 {
> > +				compatible = "fsl,imx8mp-isp";
> > +				reg = <0x32e20000 0x10000>;
> > +				interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
> > +				clocks = <&clk IMX8MP_CLK_MEDIA_ISP_ROOT>,
> > +					 <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>,
> > +					 <&clk IMX8MP_CLK_MEDIA_APB_ROOT>;
> > +				clock-names = "isp", "aclk", "hclk";
> > +				power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_ISP>;
> > +				fsl,blk-ctrl = <&media_blk_ctrl 1>;
> > +				status = "disabled";
> > +
> > +				ports {
> > +					#address-cells = <1>;
> > +					#size-cells = <0>;
> > +
> > +					port@1 {
> > +						reg = <1>;
> > +					};
> > +				};
> > +			};
> > +
> >  			dewarp: dwe@32e30000 {
> >  				compatible = "nxp,imx8mp-dw100";
> >  				reg = <0x32e30000 0x10000>;
> > @@ -1873,13 +1917,16 @@ media_blk_ctrl: blk-ctrl@32ec0000 {
> >  						  <&clk IMX8MP_CLK_MEDIA_APB>,
> >  						  <&clk IMX8MP_CLK_MEDIA_DISP1_PIX>,
> >  						  <&clk IMX8MP_CLK_MEDIA_DISP2_PIX>,
> > +						  <&clk IMX8MP_CLK_MEDIA_ISP>,
> >  						  <&clk IMX8MP_VIDEO_PLL1>;
> >  				assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>,
> >  							 <&clk IMX8MP_SYS_PLL1_800M>,
> >  							 <&clk IMX8MP_VIDEO_PLL1_OUT>,
> > -							 <&clk IMX8MP_VIDEO_PLL1_OUT>;
> > +							 <&clk IMX8MP_VIDEO_PLL1_OUT>,
> > +							 <&clk IMX8MP_SYS_PLL2_500M>;
> >  				assigned-clock-rates = <500000000>, <200000000>,
> > -						       <0>, <0>, <1039500000>;
> > +						       <0>, <0>, <0>, <500000000>,
> > +						       <1039500000>;
> 
> Isn't this one '<0>' too much? <500000000> is for IMX8MP_CLK_MEDIA_ISP, right?

Indeed. I'll send a v3.

> >  				#power-domain-cells = <1>;
> >  
> >  				lvds_bridge: bridge@5c {
> > 
> > base-commit: 7c626ce4bae1ac14f60076d00eafe71af30450ba
Adam Ford Aug. 18, 2024, 6:24 p.m. UTC | #3
On Tue, Aug 13, 2024 at 6:40 PM Laurent Pinchart
<laurent.pinchart@ideasonboard.com> wrote:
>
> From: Paul Elder <paul.elder@ideasonboard.com>
>
> The ISP supports both CSI and parallel interfaces, where port 0
> corresponds to the former and port 1 corresponds to the latter. Since
> the i.MX8MP's ISPs are connected by the parallel interface to the CSI
> receiver, set them both to port 1.
>
> Signed-off-by: Paul Elder <paul.elder@ideasonboard.com>
> Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
> Tested-by: Adam Ford <aford173@gmail.com> # imx8mp-beacon
> ---
> Changes since v2:
>
> - Assign clock parent and frequency in blk-ctrl
>
> Changes since v1:
>
> - Fix clock ordering
> - Add #address-cells and #size-cells to ports nodes
> ---
>  arch/arm64/boot/dts/freescale/imx8mp.dtsi | 51 ++++++++++++++++++++++-
>  1 file changed, 49 insertions(+), 2 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
> index d9b5c40f6460..09f1e27ee220 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
> @@ -1673,6 +1673,50 @@ isi_in_1: endpoint {
>                                 };
>                         };
>
> +                       isp_0: isp@32e10000 {
> +                               compatible = "fsl,imx8mp-isp";
> +                               reg = <0x32e10000 0x10000>;
> +                               interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
> +                               clocks = <&clk IMX8MP_CLK_MEDIA_ISP_ROOT>,
> +                                        <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>,
> +                                        <&clk IMX8MP_CLK_MEDIA_APB_ROOT>;
> +                               clock-names = "isp", "aclk", "hclk";
> +                               power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_ISP>;
> +                               fsl,blk-ctrl = <&media_blk_ctrl 0>;
> +                               status = "disabled";
> +
> +                               ports {
> +                                       #address-cells = <1>;
> +                                       #size-cells = <0>;
> +
> +                                       port@1 {
> +                                               reg = <1>;
> +                                       };
> +                               };
> +                       };
> +
> +                       isp_1: isp@32e20000 {
> +                               compatible = "fsl,imx8mp-isp";
> +                               reg = <0x32e20000 0x10000>;
> +                               interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
> +                               clocks = <&clk IMX8MP_CLK_MEDIA_ISP_ROOT>,
> +                                        <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>,
> +                                        <&clk IMX8MP_CLK_MEDIA_APB_ROOT>;
> +                               clock-names = "isp", "aclk", "hclk";
> +                               power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_ISP>;
> +                               fsl,blk-ctrl = <&media_blk_ctrl 1>;
> +                               status = "disabled";
> +
> +                               ports {
> +                                       #address-cells = <1>;
> +                                       #size-cells = <0>;
> +
> +                                       port@1 {
> +                                               reg = <1>;
> +                                       };
> +                               };
> +                       };
> +
>                         dewarp: dwe@32e30000 {
>                                 compatible = "nxp,imx8mp-dw100";
>                                 reg = <0x32e30000 0x10000>;
> @@ -1873,13 +1917,16 @@ media_blk_ctrl: blk-ctrl@32ec0000 {
>                                                   <&clk IMX8MP_CLK_MEDIA_APB>,
>                                                   <&clk IMX8MP_CLK_MEDIA_DISP1_PIX>,
>                                                   <&clk IMX8MP_CLK_MEDIA_DISP2_PIX>,
> +                                                 <&clk IMX8MP_CLK_MEDIA_ISP>,
>                                                   <&clk IMX8MP_VIDEO_PLL1>;
>                                 assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>,
>                                                          <&clk IMX8MP_SYS_PLL1_800M>,
>                                                          <&clk IMX8MP_VIDEO_PLL1_OUT>,
> -                                                        <&clk IMX8MP_VIDEO_PLL1_OUT>;
> +                                                        <&clk IMX8MP_VIDEO_PLL1_OUT>,
> +                                                        <&clk IMX8MP_SYS_PLL2_500M>;
>                                 assigned-clock-rates = <500000000>, <200000000>,
> -                                                      <0>, <0>, <1039500000>;
> +                                                      <0>, <0>, <0>, <500000000>,

Is the insertion of the extra <0> here correct?  You inserted one
clock above for IMX8MP_CLK_MEDIA_ISP, but it appears you inserted two
here.
I think this might break the IMX8MP_VIDEO_PLL1 rate and not set the
IMX8MP_CLK_MEDIA_ISP as expected.

Am I missing something?

adam

> +                                                      <1039500000>;
>                                 #power-domain-cells = <1>;
>
>                                 lvds_bridge: bridge@5c {
>
> base-commit: 7c626ce4bae1ac14f60076d00eafe71af30450ba
> --
> Regards,
>
> Laurent Pinchart
>
Laurent Pinchart Aug. 18, 2024, 7:07 p.m. UTC | #4
On Sun, Aug 18, 2024 at 01:24:01PM -0500, Adam Ford wrote:
> On Tue, Aug 13, 2024 at 6:40 PM Laurent Pinchart
> <laurent.pinchart@ideasonboard.com> wrote:
> >
> > From: Paul Elder <paul.elder@ideasonboard.com>
> >
> > The ISP supports both CSI and parallel interfaces, where port 0
> > corresponds to the former and port 1 corresponds to the latter. Since
> > the i.MX8MP's ISPs are connected by the parallel interface to the CSI
> > receiver, set them both to port 1.
> >
> > Signed-off-by: Paul Elder <paul.elder@ideasonboard.com>
> > Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
> > Tested-by: Adam Ford <aford173@gmail.com> # imx8mp-beacon
> > ---
> > Changes since v2:
> >
> > - Assign clock parent and frequency in blk-ctrl
> >
> > Changes since v1:
> >
> > - Fix clock ordering
> > - Add #address-cells and #size-cells to ports nodes
> > ---
> >  arch/arm64/boot/dts/freescale/imx8mp.dtsi | 51 ++++++++++++++++++++++-
> >  1 file changed, 49 insertions(+), 2 deletions(-)
> >
> > diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
> > index d9b5c40f6460..09f1e27ee220 100644
> > --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi
> > +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
> > @@ -1673,6 +1673,50 @@ isi_in_1: endpoint {
> >                                 };
> >                         };
> >
> > +                       isp_0: isp@32e10000 {
> > +                               compatible = "fsl,imx8mp-isp";
> > +                               reg = <0x32e10000 0x10000>;
> > +                               interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
> > +                               clocks = <&clk IMX8MP_CLK_MEDIA_ISP_ROOT>,
> > +                                        <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>,
> > +                                        <&clk IMX8MP_CLK_MEDIA_APB_ROOT>;
> > +                               clock-names = "isp", "aclk", "hclk";
> > +                               power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_ISP>;
> > +                               fsl,blk-ctrl = <&media_blk_ctrl 0>;
> > +                               status = "disabled";
> > +
> > +                               ports {
> > +                                       #address-cells = <1>;
> > +                                       #size-cells = <0>;
> > +
> > +                                       port@1 {
> > +                                               reg = <1>;
> > +                                       };
> > +                               };
> > +                       };
> > +
> > +                       isp_1: isp@32e20000 {
> > +                               compatible = "fsl,imx8mp-isp";
> > +                               reg = <0x32e20000 0x10000>;
> > +                               interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
> > +                               clocks = <&clk IMX8MP_CLK_MEDIA_ISP_ROOT>,
> > +                                        <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>,
> > +                                        <&clk IMX8MP_CLK_MEDIA_APB_ROOT>;
> > +                               clock-names = "isp", "aclk", "hclk";
> > +                               power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_ISP>;
> > +                               fsl,blk-ctrl = <&media_blk_ctrl 1>;
> > +                               status = "disabled";
> > +
> > +                               ports {
> > +                                       #address-cells = <1>;
> > +                                       #size-cells = <0>;
> > +
> > +                                       port@1 {
> > +                                               reg = <1>;
> > +                                       };
> > +                               };
> > +                       };
> > +
> >                         dewarp: dwe@32e30000 {
> >                                 compatible = "nxp,imx8mp-dw100";
> >                                 reg = <0x32e30000 0x10000>;
> > @@ -1873,13 +1917,16 @@ media_blk_ctrl: blk-ctrl@32ec0000 {
> >                                                   <&clk IMX8MP_CLK_MEDIA_APB>,
> >                                                   <&clk IMX8MP_CLK_MEDIA_DISP1_PIX>,
> >                                                   <&clk IMX8MP_CLK_MEDIA_DISP2_PIX>,
> > +                                                 <&clk IMX8MP_CLK_MEDIA_ISP>,
> >                                                   <&clk IMX8MP_VIDEO_PLL1>;
> >                                 assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>,
> >                                                          <&clk IMX8MP_SYS_PLL1_800M>,
> >                                                          <&clk IMX8MP_VIDEO_PLL1_OUT>,
> > -                                                        <&clk IMX8MP_VIDEO_PLL1_OUT>;
> > +                                                        <&clk IMX8MP_VIDEO_PLL1_OUT>,
> > +                                                        <&clk IMX8MP_SYS_PLL2_500M>;
> >                                 assigned-clock-rates = <500000000>, <200000000>,
> > -                                                      <0>, <0>, <1039500000>;
> > +                                                      <0>, <0>, <0>, <500000000>,
> 
> Is the insertion of the extra <0> here correct?  You inserted one
> clock above for IMX8MP_CLK_MEDIA_ISP, but it appears you inserted two
> here.
> I think this might break the IMX8MP_VIDEO_PLL1 rate and not set the
> IMX8MP_CLK_MEDIA_ISP as expected.
> 
> Am I missing something?

You're missing v4 :-)

> > +                                                      <1039500000>;
> >                                 #power-domain-cells = <1>;
> >
> >                                 lvds_bridge: bridge@5c {
> >
> > base-commit: 7c626ce4bae1ac14f60076d00eafe71af30450ba
Adam Ford Aug. 18, 2024, 7:17 p.m. UTC | #5
On Sun, Aug 18, 2024 at 2:07 PM Laurent Pinchart
<laurent.pinchart@ideasonboard.com> wrote:
>
> On Sun, Aug 18, 2024 at 01:24:01PM -0500, Adam Ford wrote:
> > On Tue, Aug 13, 2024 at 6:40 PM Laurent Pinchart
> > <laurent.pinchart@ideasonboard.com> wrote:
> > >
> > > From: Paul Elder <paul.elder@ideasonboard.com>
> > >
> > > The ISP supports both CSI and parallel interfaces, where port 0
> > > corresponds to the former and port 1 corresponds to the latter. Since
> > > the i.MX8MP's ISPs are connected by the parallel interface to the CSI
> > > receiver, set them both to port 1.
> > >
> > > Signed-off-by: Paul Elder <paul.elder@ideasonboard.com>
> > > Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
> > > Tested-by: Adam Ford <aford173@gmail.com> # imx8mp-beacon
> > > ---
> > > Changes since v2:
> > >
> > > - Assign clock parent and frequency in blk-ctrl
> > >
> > > Changes since v1:
> > >
> > > - Fix clock ordering
> > > - Add #address-cells and #size-cells to ports nodes
> > > ---
> > >  arch/arm64/boot/dts/freescale/imx8mp.dtsi | 51 ++++++++++++++++++++++-
> > >  1 file changed, 49 insertions(+), 2 deletions(-)
> > >
> > > diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
> > > index d9b5c40f6460..09f1e27ee220 100644
> > > --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi
> > > +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
> > > @@ -1673,6 +1673,50 @@ isi_in_1: endpoint {
> > >                                 };
> > >                         };
> > >
> > > +                       isp_0: isp@32e10000 {
> > > +                               compatible = "fsl,imx8mp-isp";
> > > +                               reg = <0x32e10000 0x10000>;
> > > +                               interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
> > > +                               clocks = <&clk IMX8MP_CLK_MEDIA_ISP_ROOT>,
> > > +                                        <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>,
> > > +                                        <&clk IMX8MP_CLK_MEDIA_APB_ROOT>;
> > > +                               clock-names = "isp", "aclk", "hclk";
> > > +                               power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_ISP>;
> > > +                               fsl,blk-ctrl = <&media_blk_ctrl 0>;
> > > +                               status = "disabled";
> > > +
> > > +                               ports {
> > > +                                       #address-cells = <1>;
> > > +                                       #size-cells = <0>;
> > > +
> > > +                                       port@1 {
> > > +                                               reg = <1>;
> > > +                                       };
> > > +                               };
> > > +                       };
> > > +
> > > +                       isp_1: isp@32e20000 {
> > > +                               compatible = "fsl,imx8mp-isp";
> > > +                               reg = <0x32e20000 0x10000>;
> > > +                               interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
> > > +                               clocks = <&clk IMX8MP_CLK_MEDIA_ISP_ROOT>,
> > > +                                        <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>,
> > > +                                        <&clk IMX8MP_CLK_MEDIA_APB_ROOT>;
> > > +                               clock-names = "isp", "aclk", "hclk";
> > > +                               power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_ISP>;
> > > +                               fsl,blk-ctrl = <&media_blk_ctrl 1>;
> > > +                               status = "disabled";
> > > +
> > > +                               ports {
> > > +                                       #address-cells = <1>;
> > > +                                       #size-cells = <0>;
> > > +
> > > +                                       port@1 {
> > > +                                               reg = <1>;
> > > +                                       };
> > > +                               };
> > > +                       };
> > > +
> > >                         dewarp: dwe@32e30000 {
> > >                                 compatible = "nxp,imx8mp-dw100";
> > >                                 reg = <0x32e30000 0x10000>;
> > > @@ -1873,13 +1917,16 @@ media_blk_ctrl: blk-ctrl@32ec0000 {
> > >                                                   <&clk IMX8MP_CLK_MEDIA_APB>,
> > >                                                   <&clk IMX8MP_CLK_MEDIA_DISP1_PIX>,
> > >                                                   <&clk IMX8MP_CLK_MEDIA_DISP2_PIX>,
> > > +                                                 <&clk IMX8MP_CLK_MEDIA_ISP>,
> > >                                                   <&clk IMX8MP_VIDEO_PLL1>;
> > >                                 assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>,
> > >                                                          <&clk IMX8MP_SYS_PLL1_800M>,
> > >                                                          <&clk IMX8MP_VIDEO_PLL1_OUT>,
> > > -                                                        <&clk IMX8MP_VIDEO_PLL1_OUT>;
> > > +                                                        <&clk IMX8MP_VIDEO_PLL1_OUT>,
> > > +                                                        <&clk IMX8MP_SYS_PLL2_500M>;
> > >                                 assigned-clock-rates = <500000000>, <200000000>,
> > > -                                                      <0>, <0>, <1039500000>;
> > > +                                                      <0>, <0>, <0>, <500000000>,
> >
> > Is the insertion of the extra <0> here correct?  You inserted one
> > clock above for IMX8MP_CLK_MEDIA_ISP, but it appears you inserted two
> > here.
> > I think this might break the IMX8MP_VIDEO_PLL1 rate and not set the
> > IMX8MP_CLK_MEDIA_ISP as expected.
> >
> > Am I missing something?
>
> You're missing v4 :-)

Sorry.  I was traveling in Europe, so I was going through the backlog
in the order they arrived.  :-)

adam

>
> > > +                                                      <1039500000>;
> > >                                 #power-domain-cells = <1>;
> > >
> > >                                 lvds_bridge: bridge@5c {
> > >
> > > base-commit: 7c626ce4bae1ac14f60076d00eafe71af30450ba
>
> --
> Regards,
>
> Laurent Pinchart
diff mbox series

Patch

diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
index d9b5c40f6460..09f1e27ee220 100644
--- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
@@ -1673,6 +1673,50 @@  isi_in_1: endpoint {
 				};
 			};
 
+			isp_0: isp@32e10000 {
+				compatible = "fsl,imx8mp-isp";
+				reg = <0x32e10000 0x10000>;
+				interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&clk IMX8MP_CLK_MEDIA_ISP_ROOT>,
+					 <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>,
+					 <&clk IMX8MP_CLK_MEDIA_APB_ROOT>;
+				clock-names = "isp", "aclk", "hclk";
+				power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_ISP>;
+				fsl,blk-ctrl = <&media_blk_ctrl 0>;
+				status = "disabled";
+
+				ports {
+					#address-cells = <1>;
+					#size-cells = <0>;
+
+					port@1 {
+						reg = <1>;
+					};
+				};
+			};
+
+			isp_1: isp@32e20000 {
+				compatible = "fsl,imx8mp-isp";
+				reg = <0x32e20000 0x10000>;
+				interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&clk IMX8MP_CLK_MEDIA_ISP_ROOT>,
+					 <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>,
+					 <&clk IMX8MP_CLK_MEDIA_APB_ROOT>;
+				clock-names = "isp", "aclk", "hclk";
+				power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_ISP>;
+				fsl,blk-ctrl = <&media_blk_ctrl 1>;
+				status = "disabled";
+
+				ports {
+					#address-cells = <1>;
+					#size-cells = <0>;
+
+					port@1 {
+						reg = <1>;
+					};
+				};
+			};
+
 			dewarp: dwe@32e30000 {
 				compatible = "nxp,imx8mp-dw100";
 				reg = <0x32e30000 0x10000>;
@@ -1873,13 +1917,16 @@  media_blk_ctrl: blk-ctrl@32ec0000 {
 						  <&clk IMX8MP_CLK_MEDIA_APB>,
 						  <&clk IMX8MP_CLK_MEDIA_DISP1_PIX>,
 						  <&clk IMX8MP_CLK_MEDIA_DISP2_PIX>,
+						  <&clk IMX8MP_CLK_MEDIA_ISP>,
 						  <&clk IMX8MP_VIDEO_PLL1>;
 				assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>,
 							 <&clk IMX8MP_SYS_PLL1_800M>,
 							 <&clk IMX8MP_VIDEO_PLL1_OUT>,
-							 <&clk IMX8MP_VIDEO_PLL1_OUT>;
+							 <&clk IMX8MP_VIDEO_PLL1_OUT>,
+							 <&clk IMX8MP_SYS_PLL2_500M>;
 				assigned-clock-rates = <500000000>, <200000000>,
-						       <0>, <0>, <1039500000>;
+						       <0>, <0>, <0>, <500000000>,
+						       <1039500000>;
 				#power-domain-cells = <1>;
 
 				lvds_bridge: bridge@5c {