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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: 4FTjqY1pctc5IrfDxEH/T8yMyTzWIZHfp2o91rA9Vi4ZsR/vlcl2NhZtJ7NkyZvcMDnBpG1etds7TdEnn7YxrgrV7xTvs+Vn4WfK+r6ugjMRkDBk3ulHHRfo2CqSxzQKdg3nsILW0s5HcP655j4RTqRaVorlB3dcn7aU4KCeEoNBI5iV9qfPtFg1gX04w8UCLs/nwAv0Q/fROz7TZEhgSHjlzsuH+KipIQ+BT8MghmxEM6E1kpPa+3qvjKjRsX294oEqp4y4JM1B+bkZQMX/pYVn5cLDE2Dzv4Q38hD4CpO67/aJ+XZR0SeL7lZp+N+KpICv9DyRH4Qp4S7gIPacLRsC8QeTI6kvQc1Dvkl01Ny/DO5pSL0LlZrHDw6xp6Z7K8enJ/IAcxbtUjyvpzo2/AXZYybpQ7YW4tbEOd3SQIe4uXsCYPP/F0d7efBFfTHR3W9bMtwKhbz9xSMkSI01T5CpZpk5hxX0IDPc+HCv4NoH38hLZTobOgR5eNuappceQjTGg4CChM0obWtfGLG+dXdyTLaOxfjKJMn2yVU+zglloiEnd6aOUpz+dZ9Og8oFxKRJmDdhaLC2vcwpQijEPo2k0RYvK3KRTb0hTrsbVK0eDsVx3GD2cF708T1xkCfnABLR6JCsvimuwGifFmfhRTal9yc//lvm/2utm1OvDFjcqq0lOgVvjYIxsAnZt5NHt6NS+rxGZ88O0NWvUTVhAxCOAvRdXxf4wGU6g0GqG/WzMyxS5Q+lPRIE9bEJ/ZJ8P7EUD0Tc+94BvIXWIMWO1ArYRwQug7/fOFoLFpgW6VrluB9/VwlM4HOVUI1dIw1TK2pbx2G8t3Z2gfaY/kk8BTU5LsI8e5hdWmXoN2XebBsH+N19F/XB7CKKlNzt9OuewmcQvHUH/Duup/6MmiimbuyX8x2risLBlHEKJF2fw4fQPU1ME+XAIwKKdl2X/VaeEnqoX4Ipjjor7sjySEJnABWtCh2W/GBSOaKPAk7kEfYAvO9hmIW7s5hlt/iLRB8syGcp9RBoUBPlWdYe6+z4VNcM4Aed8OLvodJvep6sLr0YDA2qr6Ao0tS8swLJskXIWiiTPXWCWFykiq50rkI+/xLUaZM8/41avMUfX6IjRb/zpMieYs9VHpD9tUGU3xv7lK91qXvT3mj9nSCyWF/oABv2pKV4TocPNJHfxf7RTBGXogQv8jiGPAr3ASNvRiJSfygwc8L2TcFWuLKd1oOHzf4xpt+OoBKShUEOVoMUG8uydR+VA/lCsfXNxWRvQBbAzGcDcsxRETnH61RCktyfHwhIQPON2DJFfhgG1w1LP1AE3Knye4ctTF6qkDYP+nWPxmuKpVi1tz/UEVFUtmYGA+1V5YgtDM89WDWVb+ybAmk+/g3YNyoHFd3f+oC5W4B6MZWGCcbFjVUuXUiiM/ImOY0zoscO3pvgYl4lK4q3hk/8wFQ9rvyXmQJvwmYPpzYaiOfaDacebcr7vafd0h4qqR3zbadGQpq8xhYNjvS8XsrKI7wfc5RWBIw5W0SvzGVG1P02UUKZQ55HeybjGSOSqva7iPsuv6vZEkk3WeQ8sdNRCb095FTtR7iAhQRe4By8 X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: 0c64a7ed-5e1e-42a2-41c3-08dccd49bb5d X-MS-Exchange-CrossTenant-AuthSource: DU0PR04MB9496.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 05 Sep 2024 01:26:14.2144 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: l8TGSQNlEzplNpgO2TJOXa6gNBZRdXzitH57Hfw7wbFtrofBOiquX+HB0B238nyGp6C24S+zGLie5WJn7xsKDQ== X-MS-Exchange-Transport-CrossTenantHeadersStamped: DU4PR04MB10339 From: Haibo Chen The flexspi on imx8ulp only has 16 LUTs, different with others which have up to 32 LUTs. Add a separate compatible string and nxp_fspi_devtype_data to support flexspi on imx8ulp. Signed-off-by: Haibo Chen --- drivers/spi/spi-nxp-fspi.c | 54 ++++++++++++++++++++++++-------------- 1 file changed, 35 insertions(+), 19 deletions(-) diff --git a/drivers/spi/spi-nxp-fspi.c b/drivers/spi/spi-nxp-fspi.c index fd1816befcd8..64af89323802 100644 --- a/drivers/spi/spi-nxp-fspi.c +++ b/drivers/spi/spi-nxp-fspi.c @@ -57,13 +57,6 @@ #include #include -/* - * The driver only uses one single LUT entry, that is updated on - * each call of exec_op(). Index 0 is preset at boot with a basic - * read operation, so let's use the last entry (31). - */ -#define SEQID_LUT 31 - /* Registers used by the driver */ #define FSPI_MCR0 0x00 #define FSPI_MCR0_AHB_TIMEOUT(x) ((x) << 24) @@ -263,9 +256,6 @@ #define FSPI_TFDR 0x180 #define FSPI_LUT_BASE 0x200 -#define FSPI_LUT_OFFSET (SEQID_LUT * 4 * 4) -#define FSPI_LUT_REG(idx) \ - (FSPI_LUT_BASE + FSPI_LUT_OFFSET + (idx) * 4) /* register map end */ @@ -341,6 +331,7 @@ struct nxp_fspi_devtype_data { unsigned int txfifo; unsigned int ahb_buf_size; unsigned int quirks; + unsigned int lut_num; bool little_endian; }; @@ -349,6 +340,7 @@ static struct nxp_fspi_devtype_data lx2160a_data = { .txfifo = SZ_1K, /* (128 * 64 bits) */ .ahb_buf_size = SZ_2K, /* (256 * 64 bits) */ .quirks = 0, + .lut_num = 32, .little_endian = true, /* little-endian */ }; @@ -357,6 +349,7 @@ static struct nxp_fspi_devtype_data imx8mm_data = { .txfifo = SZ_1K, /* (128 * 64 bits) */ .ahb_buf_size = SZ_2K, /* (256 * 64 bits) */ .quirks = 0, + .lut_num = 32, .little_endian = true, /* little-endian */ }; @@ -365,6 +358,7 @@ static struct nxp_fspi_devtype_data imx8qxp_data = { .txfifo = SZ_1K, /* (128 * 64 bits) */ .ahb_buf_size = SZ_2K, /* (256 * 64 bits) */ .quirks = 0, + .lut_num = 32, .little_endian = true, /* little-endian */ }; @@ -373,6 +367,16 @@ static struct nxp_fspi_devtype_data imx8dxl_data = { .txfifo = SZ_1K, /* (128 * 64 bits) */ .ahb_buf_size = SZ_2K, /* (256 * 64 bits) */ .quirks = FSPI_QUIRK_USE_IP_ONLY, + .lut_num = 32, + .little_endian = true, /* little-endian */ +}; + +static struct nxp_fspi_devtype_data imx8ulp_data = { + .rxfifo = SZ_512, /* (64 * 64 bits) */ + .txfifo = SZ_1K, /* (128 * 64 bits) */ + .ahb_buf_size = SZ_2K, /* (256 * 64 bits) */ + .quirks = 0, + .lut_num = 16, .little_endian = true, /* little-endian */ }; @@ -544,6 +548,8 @@ static void nxp_fspi_prepare_lut(struct nxp_fspi *f, void __iomem *base = f->iobase; u32 lutval[4] = {}; int lutidx = 1, i; + u32 lut_offset = (f->devtype_data->lut_num - 1) * 4 * 4; + u32 target_lut_reg; /* cmd */ lutval[0] |= LUT_DEF(0, LUT_CMD, LUT_PAD(op->cmd.buswidth), @@ -588,8 +594,10 @@ static void nxp_fspi_prepare_lut(struct nxp_fspi *f, fspi_writel(f, FSPI_LCKER_UNLOCK, f->iobase + FSPI_LCKCR); /* fill LUT */ - for (i = 0; i < ARRAY_SIZE(lutval); i++) - fspi_writel(f, lutval[i], base + FSPI_LUT_REG(i)); + for (i = 0; i < ARRAY_SIZE(lutval); i++) { + target_lut_reg = FSPI_LUT_BASE + lut_offset + i * 4; + fspi_writel(f, lutval[i], base + target_lut_reg); + } dev_dbg(f->dev, "CMD[%02x] lutval[0:%08x 1:%08x 2:%08x 3:%08x], size: 0x%08x\n", op->cmd.opcode, lutval[0], lutval[1], lutval[2], lutval[3], op->data.nbytes); @@ -874,7 +882,7 @@ static int nxp_fspi_do_op(struct nxp_fspi *f, const struct spi_mem_op *op) void __iomem *base = f->iobase; int seqnum = 0; int err = 0; - u32 reg; + u32 reg, seqid_lut; reg = fspi_readl(f, base + FSPI_IPRXFCR); /* invalid RXFIFO first */ @@ -890,8 +898,9 @@ static int nxp_fspi_do_op(struct nxp_fspi *f, const struct spi_mem_op *op) * the LUT at each exec_op() call. And also specify the DATA * length, since it's has not been specified in the LUT. */ + seqid_lut = f->devtype_data->lut_num - 1; fspi_writel(f, op->data.nbytes | - (SEQID_LUT << FSPI_IPCR1_SEQID_SHIFT) | + (seqid_lut << FSPI_IPCR1_SEQID_SHIFT) | (seqnum << FSPI_IPCR1_SEQNUM_SHIFT), base + FSPI_IPCR1); @@ -1015,7 +1024,7 @@ static int nxp_fspi_default_setup(struct nxp_fspi *f) { void __iomem *base = f->iobase; int ret, i; - u32 reg; + u32 reg, seqid_lut; /* disable and unprepare clock to avoid glitch pass to controller */ nxp_fspi_clk_disable_unprep(f); @@ -1090,11 +1099,17 @@ static int nxp_fspi_default_setup(struct nxp_fspi *f) fspi_writel(f, reg, base + FSPI_FLSHB1CR1); fspi_writel(f, reg, base + FSPI_FLSHB2CR1); + /* + * The driver only uses one single LUT entry, that is updated on + * each call of exec_op(). Index 0 is preset at boot with a basic + * read operation, so let's use the last entry (31 or 15). + */ + seqid_lut = f->devtype_data->lut_num - 1; /* AHB Read - Set lut sequence ID for all CS. */ - fspi_writel(f, SEQID_LUT, base + FSPI_FLSHA1CR2); - fspi_writel(f, SEQID_LUT, base + FSPI_FLSHA2CR2); - fspi_writel(f, SEQID_LUT, base + FSPI_FLSHB1CR2); - fspi_writel(f, SEQID_LUT, base + FSPI_FLSHB2CR2); + fspi_writel(f, seqid_lut, base + FSPI_FLSHA1CR2); + fspi_writel(f, seqid_lut, base + FSPI_FLSHA2CR2); + fspi_writel(f, seqid_lut, base + FSPI_FLSHB1CR2); + fspi_writel(f, seqid_lut, base + FSPI_FLSHB2CR2); f->selected = -1; @@ -1289,6 +1304,7 @@ static const struct of_device_id nxp_fspi_dt_ids[] = { { .compatible = "nxp,imx8mp-fspi", .data = (void *)&imx8mm_data, }, { .compatible = "nxp,imx8qxp-fspi", .data = (void *)&imx8qxp_data, }, { .compatible = "nxp,imx8dxl-fspi", .data = (void *)&imx8dxl_data, }, + { .compatible = "nxp,imx8ulp-fspi", .data = (void *)&imx8ulp_data, }, { /* sentinel */ } }; MODULE_DEVICE_TABLE(of, nxp_fspi_dt_ids);