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b=TjIAKZ8Hp0Yyeo0I5qc0a1k5SiDNjLKM0IEhr2lycMsrwm65pWVbyKaPQ3B3YPPwgWcG9LAGzMOHz2mrMK3N7hfUULrxdcJRSjsCbZ/BQ6n0VivXnGHkYrPnUNHnF2HrEIjp9EZjffgEx5MFx67lKfrs1KAdDksKnKWHR0Rkg0hDBnNd38MMefHHxKJsfHAO8AsUu3k4/bhGT9M0i0wAdx/lcoiDUk85YQuZHDYk1psuNESokP9GU5bkBNzpu7P2udnlxxjJ3WxPtLfhpZLH9gK69ujrubIDSLK2ssCEBHVbytKES+RZZNQM6xRg8ExNGdQtvFfayItv6109XPbw0A== Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=nxp.com; Received: from DU0PR04MB9496.eurprd04.prod.outlook.com (2603:10a6:10:32d::19) by GV1PR04MB10306.eurprd04.prod.outlook.com (2603:10a6:150:1c9::22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7918.25; Thu, 5 Sep 2024 09:45:02 +0000 Received: from DU0PR04MB9496.eurprd04.prod.outlook.com ([fe80::4fa3:7420:14ed:5334]) by DU0PR04MB9496.eurprd04.prod.outlook.com ([fe80::4fa3:7420:14ed:5334%4]) with mapi id 15.20.7918.024; Thu, 5 Sep 2024 09:45:02 +0000 From: haibo.chen@nxp.com To: han.xu@nxp.com, yogeshgaur.83@gmail.com, broonie@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, shawnguo@kernel.org, s.hauer@pengutronix.de Cc: kernel@pengutronix.de, festevam@gmail.com, singh.kuldeep87k@gmail.com, hs@denx.de, linux-spi@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, haibo.chen@nxp.com, peng.fan@nxp.com, stable@kernel.org Subject: [PATCH v3 2/4] spi: fspi: involve lut_num for struct nxp_fspi_devtype_data Date: Thu, 5 Sep 2024 17:43:36 +0800 Message-Id: <20240905094338.1986871-3-haibo.chen@nxp.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240905094338.1986871-1-haibo.chen@nxp.com> References: <20240905094338.1986871-1-haibo.chen@nxp.com> X-ClientProxiedBy: SG2P153CA0020.APCP153.PROD.OUTLOOK.COM (2603:1096:4:c7::7) To DU0PR04MB9496.eurprd04.prod.outlook.com (2603:10a6:10:32d::19) Precedence: bulk X-Mailing-List: imx@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DU0PR04MB9496:EE_|GV1PR04MB10306:EE_ X-MS-Office365-Filtering-Correlation-Id: 452c234d-70a5-4f1e-df8b-08dccd8f6a18 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|7416014|52116014|366016|1800799024|38350700014; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: FBmyjqUSCl0B+w2zirs0SsHOqDBl7MHRgmCZ6vLSvNeBFgWwgZoicm67PTij+hMocfLLZjH0nt9DIGkxHdu+mLNmWwkCWuvohMzGa4iRZWpHv0X/VA+9kej6+GaQdIUE8ZyF7G5PtM2VELREpLg3T0004BwO9aksWY4pVZb66VoMwkFv3hlH1rVl2VNjtqrIbHPKoAkDZ/1XL3cdBdiYTs2E0fWGY6V9bkhlNMlDWmevSa3U2ZTxahh836dFA8vnPvdRrkZefHetTJwwloidD/V7ZuW7tk/346rykDaZ3Bip1Be055sBTMZWOezkmb2O7oPrLytjB09BZeaKikScoG5W3vQVImf4+SmgqhIpU9LeXB0azXJ0NFXdE88vhFZDUM+dTTwuiFUM0/KwHCftFJT/7KUb9u5QFtbBJJiV7s98zs3ReEMWt1vMcTd1y4Jbbaxk+92BaN2XJkQbnJRQiTGPWyYtKEc3fDpYwCCtCA6N8YPhWpMjIf7O7KftmPnPoEuePXqoDV+K6IVr+P8hRscYOi4ipEOFx/Y+ibzDkHriSli81Tya3AckbdFiXOvTSOnQNbh0A/ZCmXwi6aFBHiurnbb8SV+o+m2vdcMB/T+Lj+DlR/3hB191PiilO7d6P91DJVlyDg6ijbzzZyO5rwZxTLCRJsnxrxjjTm1Y0ZwDzLwa8S7uO71Z6UFt4bubuREcgWTuBoMhadQCig2TkLtamlaYYtDn0GjqVJ+bcGpfp26dqPZuyy5fmSTprHL7X5nVTmu0a9z2/EVU9FMyAlRg2lk5ZhxGFP8nMFYPkUZFQF7d1efwYPu9T+E9/MABiynAYovKr8oyrkWTckbUc0Rju/X1P0BPHmAP+vbI03/KbNJAcO7GAsZ+pmy/ArLA6l1OTefqRtoMjYqt53xuCKV0v14QGTp92WMTeSf1U0BFKDWvFMHiqaasRnv5SnH+QjwSDcHVzAivxDzVmctkroKSgOEFMwayrsB7QZfie9Q4mK+AOokgYGeyFfo29vzvaLSoIlCwEe7bnK5r1mPFcwX98kCd3RENT8nOY1qa8ObeL5PL6yFpdWUgmR/uriX6EfrNwSxrpTGHu/VUG6sc4RVTpPl2s8B2u2GCSWhFGW9l32piOwTJjDUIyOLRgqpeQ4xLhyM8OW26sc1Ph3rdzovACTIGyluh08IOS9vMvQoWhv0OMgqmXuiERtNv9qX5GFrCU97ZE4wJ+Xon8oI5LgrQHvM3JayLA8BmJ56Kg2j8cuP7MDh7oUWtzG1ofSnMjMuPgTttEipgW5X/heYYcuVS8nU+C048E4ynveKQmYw48ny56z/UibhBkON4zqvbTBz8FyJNt6iyMES/Ww2RDjNC6V0/CVJ4WWLRMA/ChVbF0+YYiM3dbRrZVzFdq16WHP4hJ81mWaWW5UfdF0flWBRy2IIOb9K7PBDb8nmBjGBH7uGvodLkgRoLSo+phCjOaGPaLDXN9UIi4UgnLdTnwEy1bH4A1C8h02wZ0zn38H0jJJm/KWpr77BZVCn4tstTfGcEVLfjcV1w+aMseO2A3lxnpS7R+MxR3B61oydaKeQAoU+GEKN5ADUEjURDqdwy X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: 452c234d-70a5-4f1e-df8b-08dccd8f6a18 X-MS-Exchange-CrossTenant-AuthSource: DU0PR04MB9496.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 05 Sep 2024 09:45:02.5791 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: HbevghjBZESYmCOHFDFGN7wJ6QsOpQtaFhwmYinfAUgLXNMyKMgaadEIBW8ARVy/mxmgniCMGL45cF0wJFJjhg== X-MS-Exchange-Transport-CrossTenantHeadersStamped: GV1PR04MB10306 From: Haibo Chen The flexspi on different SoCs may have different number of LUTs. So involve lut_num in nxp_fspi_devtype_data to make distinguish. This patch prepare for the adding of imx8ulp. Fixes: ef89fd56bdfc ("arm64: dts: imx8ulp: add flexspi node") Cc: stable@kernel.org Signed-off-by: Haibo Chen Reviewed-by: Frank Li --- drivers/spi/spi-nxp-fspi.c | 44 ++++++++++++++++++++++---------------- 1 file changed, 25 insertions(+), 19 deletions(-) diff --git a/drivers/spi/spi-nxp-fspi.c b/drivers/spi/spi-nxp-fspi.c index fd1816befcd8..f42c14d80289 100644 --- a/drivers/spi/spi-nxp-fspi.c +++ b/drivers/spi/spi-nxp-fspi.c @@ -57,13 +57,6 @@ #include #include -/* - * The driver only uses one single LUT entry, that is updated on - * each call of exec_op(). Index 0 is preset at boot with a basic - * read operation, so let's use the last entry (31). - */ -#define SEQID_LUT 31 - /* Registers used by the driver */ #define FSPI_MCR0 0x00 #define FSPI_MCR0_AHB_TIMEOUT(x) ((x) << 24) @@ -263,9 +256,6 @@ #define FSPI_TFDR 0x180 #define FSPI_LUT_BASE 0x200 -#define FSPI_LUT_OFFSET (SEQID_LUT * 4 * 4) -#define FSPI_LUT_REG(idx) \ - (FSPI_LUT_BASE + FSPI_LUT_OFFSET + (idx) * 4) /* register map end */ @@ -341,6 +331,7 @@ struct nxp_fspi_devtype_data { unsigned int txfifo; unsigned int ahb_buf_size; unsigned int quirks; + unsigned int lut_num; bool little_endian; }; @@ -349,6 +340,7 @@ static struct nxp_fspi_devtype_data lx2160a_data = { .txfifo = SZ_1K, /* (128 * 64 bits) */ .ahb_buf_size = SZ_2K, /* (256 * 64 bits) */ .quirks = 0, + .lut_num = 32, .little_endian = true, /* little-endian */ }; @@ -357,6 +349,7 @@ static struct nxp_fspi_devtype_data imx8mm_data = { .txfifo = SZ_1K, /* (128 * 64 bits) */ .ahb_buf_size = SZ_2K, /* (256 * 64 bits) */ .quirks = 0, + .lut_num = 32, .little_endian = true, /* little-endian */ }; @@ -365,6 +358,7 @@ static struct nxp_fspi_devtype_data imx8qxp_data = { .txfifo = SZ_1K, /* (128 * 64 bits) */ .ahb_buf_size = SZ_2K, /* (256 * 64 bits) */ .quirks = 0, + .lut_num = 32, .little_endian = true, /* little-endian */ }; @@ -373,6 +367,7 @@ static struct nxp_fspi_devtype_data imx8dxl_data = { .txfifo = SZ_1K, /* (128 * 64 bits) */ .ahb_buf_size = SZ_2K, /* (256 * 64 bits) */ .quirks = FSPI_QUIRK_USE_IP_ONLY, + .lut_num = 32, .little_endian = true, /* little-endian */ }; @@ -544,6 +539,8 @@ static void nxp_fspi_prepare_lut(struct nxp_fspi *f, void __iomem *base = f->iobase; u32 lutval[4] = {}; int lutidx = 1, i; + u32 lut_offset = (f->devtype_data->lut_num - 1) * 4 * 4; + u32 target_lut_reg; /* cmd */ lutval[0] |= LUT_DEF(0, LUT_CMD, LUT_PAD(op->cmd.buswidth), @@ -588,8 +585,10 @@ static void nxp_fspi_prepare_lut(struct nxp_fspi *f, fspi_writel(f, FSPI_LCKER_UNLOCK, f->iobase + FSPI_LCKCR); /* fill LUT */ - for (i = 0; i < ARRAY_SIZE(lutval); i++) - fspi_writel(f, lutval[i], base + FSPI_LUT_REG(i)); + for (i = 0; i < ARRAY_SIZE(lutval); i++) { + target_lut_reg = FSPI_LUT_BASE + lut_offset + i * 4; + fspi_writel(f, lutval[i], base + target_lut_reg); + } dev_dbg(f->dev, "CMD[%02x] lutval[0:%08x 1:%08x 2:%08x 3:%08x], size: 0x%08x\n", op->cmd.opcode, lutval[0], lutval[1], lutval[2], lutval[3], op->data.nbytes); @@ -874,7 +873,7 @@ static int nxp_fspi_do_op(struct nxp_fspi *f, const struct spi_mem_op *op) void __iomem *base = f->iobase; int seqnum = 0; int err = 0; - u32 reg; + u32 reg, seqid_lut; reg = fspi_readl(f, base + FSPI_IPRXFCR); /* invalid RXFIFO first */ @@ -890,8 +889,9 @@ static int nxp_fspi_do_op(struct nxp_fspi *f, const struct spi_mem_op *op) * the LUT at each exec_op() call. And also specify the DATA * length, since it's has not been specified in the LUT. */ + seqid_lut = f->devtype_data->lut_num - 1; fspi_writel(f, op->data.nbytes | - (SEQID_LUT << FSPI_IPCR1_SEQID_SHIFT) | + (seqid_lut << FSPI_IPCR1_SEQID_SHIFT) | (seqnum << FSPI_IPCR1_SEQNUM_SHIFT), base + FSPI_IPCR1); @@ -1015,7 +1015,7 @@ static int nxp_fspi_default_setup(struct nxp_fspi *f) { void __iomem *base = f->iobase; int ret, i; - u32 reg; + u32 reg, seqid_lut; /* disable and unprepare clock to avoid glitch pass to controller */ nxp_fspi_clk_disable_unprep(f); @@ -1090,11 +1090,17 @@ static int nxp_fspi_default_setup(struct nxp_fspi *f) fspi_writel(f, reg, base + FSPI_FLSHB1CR1); fspi_writel(f, reg, base + FSPI_FLSHB2CR1); + /* + * The driver only uses one single LUT entry, that is updated on + * each call of exec_op(). Index 0 is preset at boot with a basic + * read operation, so let's use the last entry. + */ + seqid_lut = f->devtype_data->lut_num - 1; /* AHB Read - Set lut sequence ID for all CS. */ - fspi_writel(f, SEQID_LUT, base + FSPI_FLSHA1CR2); - fspi_writel(f, SEQID_LUT, base + FSPI_FLSHA2CR2); - fspi_writel(f, SEQID_LUT, base + FSPI_FLSHB1CR2); - fspi_writel(f, SEQID_LUT, base + FSPI_FLSHB2CR2); + fspi_writel(f, seqid_lut, base + FSPI_FLSHA1CR2); + fspi_writel(f, seqid_lut, base + FSPI_FLSHA2CR2); + fspi_writel(f, seqid_lut, base + FSPI_FLSHB1CR2); + fspi_writel(f, seqid_lut, base + FSPI_FLSHB2CR2); f->selected = -1;