Message ID | 20241011201645.797394-4-afd@ti.com (mailing list archive) |
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State | New |
Headers | show
Received: from lelv0142.ext.ti.com (lelv0142.ext.ti.com [198.47.23.249]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3552C19CC10 for <imx@lists.linux.dev>; Fri, 11 Oct 2024 20:17:12 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.23.249 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1728677834; cv=none; b=VIoqYsCCG+CRFTXao8dwHY0CsY5mBDSJffuVR7mBcuSiF1Y3iK9aJ1xwKxKDbjqko8bKTAhPSPd3TDyypKsOw1YxqTya1Pmuhz26ROu3G/AUlifd5E16imd5qJ3akDmiTvxPsOmCJj1wOLQSRYjNyg8b7U7QLtkYx3fdLjJ8ja4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1728677834; c=relaxed/simple; bh=NJN1GNR5FglhPaWtGVRtLSZ+9nR3k3nYEOBv/xPhWtw=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=mW2XX4Cv3lwctIdfN292JdlSPkp5joCF964QWDbWORhRzExFygq8ezHBqnHsO7wRAdo3YSsKsIYnS910Lo7EBsRHtDavfNisXftvjU0nZxgsGiq21+5DLXe8ARVM/JsqEVYo+LNBlGMvy+FTXqRE8qIReH7IujCfVy4oMnU0YFc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=nCtWOOoh; arc=none smtp.client-ip=198.47.23.249 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="nCtWOOoh" Received: from fllv0034.itg.ti.com ([10.64.40.246]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id 49BKGnMO029277; Fri, 11 Oct 2024 15:16:49 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1728677809; bh=1hB+Rsl8dEIP80gJg1dRpUGGywa9yjHgvJWWFP9MDZc=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=nCtWOOohW6BZJk/VXaTP8AdC7WcIZTgcYxv9cw7f2CZdannIIeHVEV83yh+98u5CV d4IsyC1ZdrXTmQ4jkJBRIIqzdzEUYF1ZYivTiq12oRI6JJT5p2SqP+a7ewccwrahMX avy4vussnrnUJdJqbPGAUKKlFtDNhOu9gSPFOzeQ= Received: from DFLE111.ent.ti.com (dfle111.ent.ti.com [10.64.6.32]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 49BKGn8a106998 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Fri, 11 Oct 2024 15:16:49 -0500 Received: from DFLE108.ent.ti.com (10.64.6.29) by DFLE111.ent.ti.com (10.64.6.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Fri, 11 Oct 2024 15:16:48 -0500 Received: from lelvsmtp6.itg.ti.com (10.180.75.249) by DFLE108.ent.ti.com (10.64.6.29) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Fri, 11 Oct 2024 15:16:49 -0500 Received: from fllvsmtp7.itg.ti.com ([10.249.42.149]) by lelvsmtp6.itg.ti.com (8.15.2/8.15.2) with ESMTP id 49BKGkCJ102075; Fri, 11 Oct 2024 15:16:48 -0500 From: Andrew Davis <afd@ti.com> To: Andre Przywara <andre.przywara@arm.com>, Russell King <linux@armlinux.org.uk>, Shawn Guo <shawnguo@kernel.org>, Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix Kernel Team <kernel@pengutronix.de>, Fabio Estevam <festevam@gmail.com>, Andrew Lunn <andrew@lunn.ch>, Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>, Gregory Clement <gregory.clement@bootlin.com>, Daniel Mack <daniel@zonque.org>, Haojian Zhuang <haojian.zhuang@gmail.com>, Robert Jarzmik <robert.jarzmik@free.fr> CC: <linux-arm-kernel@lists.infradead.org>, <linux-kernel@vger.kernel.org>, <imx@lists.linux.dev>, Andrew Davis <afd@ti.com> Subject: [PATCH v3 3/6] ARM: pxa: Switch to new sys-off handler API Date: Fri, 11 Oct 2024 15:16:42 -0500 Message-ID: <20241011201645.797394-4-afd@ti.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20241011201645.797394-1-afd@ti.com> References: <20241011201645.797394-1-afd@ti.com> Precedence: bulk X-Mailing-List: imx@lists.linux.dev List-Id: <imx.lists.linux.dev> List-Subscribe: <mailto:imx+subscribe@lists.linux.dev> List-Unsubscribe: <mailto:imx+unsubscribe@lists.linux.dev> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea |
Series |
Switch more ARM plats to sys-off handler API
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expand
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diff --git a/arch/arm/mach-pxa/spitz.c b/arch/arm/mach-pxa/spitz.c index 33533e35720f8..c0b1f7e6be874 100644 --- a/arch/arm/mach-pxa/spitz.c +++ b/arch/arm/mach-pxa/spitz.c @@ -1096,7 +1096,7 @@ static void __init spitz_init(void) software_node_register(&spitz_scoop_2_gpiochip_node); init_gpio_reset(SPITZ_GPIO_ON_RESET, 1, 0); - pm_power_off = spitz_poweroff; + register_platform_power_off(spitz_poweroff); PMCR = 0x00;
Kernel now supports chained power-off handlers. Use register_platform_power_off() that registers a platform level power-off handler. Legacy pm_power_off() will be removed once all drivers and archs are converted to the new sys-off API. Signed-off-by: Andrew Davis <afd@ti.com> --- arch/arm/mach-pxa/spitz.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)