| Message ID | 20241012073543.1388069-3-victor.liu@nxp.com (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | Add ITE IT6263 LVDS to HDMI converter support | expand |
On 10/12/24 9:35 AM, Liu Ying wrote: > Add a panel-timing node to panel-lvds node to override any fixed > display modes written in a panel driver. This way, 74.25MHz clock > frequency specified in panel-timing node may accommodate 7-fold > 519.75MHz "media_ldb" clock which is derived from 1.0395GHz > "video_pll1" clock. > > This should suppress this LDB driver warning: > [ 17.923709] fsl-ldb 32ec0000.blk-ctrl:bridge@5c: Configured LDB clock (72400000 Hz) does not match requested LVDS clock: 506800000 Hz > > This also makes the display mode used by the panel pass mode validation > against pixel clock rate and "media_ldb" clock rate in a certain display > driver. > > Fixes: 326d86e197fc ("arm64: dts: imx8mp-phyboard-pollux-rdk: add etml panel support") > Signed-off-by: Liu Ying <victor.liu@nxp.com> > --- > v2: > * No change. > > .../dts/freescale/imx8mp-phyboard-pollux-rdk.dts | 15 +++++++++++++++ > 1 file changed, 15 insertions(+) > > diff --git a/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dts b/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dts > index 50debe821c42..20cb5363cccb 100644 > --- a/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dts > +++ b/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dts > @@ -37,6 +37,21 @@ panel1_lvds: panel-lvds { > backlight = <&backlight_lvds>; > power-supply = <®_vcc_3v3_sw>; > > + panel-timing { > + clock-frequency = <74250000>; > + hactive = <1280>; > + vactive = <800>; > + hfront-porch = <72>; > + hback-porch = <86>; > + hsync-len = <2>; > + vfront-porch = <15>; > + vback-porch = <21>; > + vsync-len = <2>; > + hsync-active = <0>; > + vsync-active = <0>; > + de-active = <1>; > + }; There is an existing entry for this panel in panel-simple.c , please do not duplicate timings in the DT: drivers/gpu/drm/panel/panel-simple.c:static const struct panel_desc edt_etml1010g3dra = { drivers/gpu/drm/panel/panel-simple.c: .timings = &edt_etml1010g3dra_timing, drivers/gpu/drm/panel/panel-simple.c: .compatible = "edt,etml1010g3dra",
diff --git a/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dts b/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dts index 50debe821c42..20cb5363cccb 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dts @@ -37,6 +37,21 @@ panel1_lvds: panel-lvds { backlight = <&backlight_lvds>; power-supply = <®_vcc_3v3_sw>; + panel-timing { + clock-frequency = <74250000>; + hactive = <1280>; + vactive = <800>; + hfront-porch = <72>; + hback-porch = <86>; + hsync-len = <2>; + vfront-porch = <15>; + vback-porch = <21>; + vsync-len = <2>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + }; + port { panel1_in: endpoint { remote-endpoint = <&ldb_lvds_ch1>;
Add a panel-timing node to panel-lvds node to override any fixed display modes written in a panel driver. This way, 74.25MHz clock frequency specified in panel-timing node may accommodate 7-fold 519.75MHz "media_ldb" clock which is derived from 1.0395GHz "video_pll1" clock. This should suppress this LDB driver warning: [ 17.923709] fsl-ldb 32ec0000.blk-ctrl:bridge@5c: Configured LDB clock (72400000 Hz) does not match requested LVDS clock: 506800000 Hz This also makes the display mode used by the panel pass mode validation against pixel clock rate and "media_ldb" clock rate in a certain display driver. Fixes: 326d86e197fc ("arm64: dts: imx8mp-phyboard-pollux-rdk: add etml panel support") Signed-off-by: Liu Ying <victor.liu@nxp.com> --- v2: * No change. .../dts/freescale/imx8mp-phyboard-pollux-rdk.dts | 15 +++++++++++++++ 1 file changed, 15 insertions(+)