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Fri, 18 Oct 2024 09:52:32 +0000 Received: from PAXPR04MB8459.eurprd04.prod.outlook.com ([fe80::165a:30a2:5835:9630]) by PAXPR04MB8459.eurprd04.prod.outlook.com ([fe80::165a:30a2:5835:9630%6]) with mapi id 15.20.8069.016; Fri, 18 Oct 2024 09:52:32 +0000 From: "Peng Fan (OSS)" Date: Fri, 18 Oct 2024 18:00:55 +0800 Subject: [PATCH v2 1/4] clk: imx: lpcg-scu: SW workaround for errata (e10858) Message-Id: <20241018-imx-clk-v1-v2-1-92c0b66ca970@nxp.com> References: <20241018-imx-clk-v1-v2-0-92c0b66ca970@nxp.com> In-Reply-To: <20241018-imx-clk-v1-v2-0-92c0b66ca970@nxp.com> To: Abel Vesa , Michael Turquette , Stephen Boyd , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , Aisheng Dong Cc: linux-clk@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Peng Fan X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1729245675; l=3168; i=peng.fan@nxp.com; s=20230812; h=from:subject:message-id; bh=5lV6Fnymwi08mNJOqfNiqBqacUaEGvCOefJyeSXwdDg=; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?utf-8?q?Ttbf1zsYoOOlcz0+FhG0HIiD5dCT?= =?utf-8?q?vmLwX2AaY84KvMn3PjP0GY6LHwixLmScsi6VwwXKAqn8/fhH54e4eT0VSujytk/mi?= =?utf-8?q?z/pscJMGjQOduF3X9dI7HGlSSeZmoL+830pLJ2EAT6/OJ05UnxfrMpftZB3PREHHP?= =?utf-8?q?mB6SkkM6kZKZLgYGTcqmZGYCsTyUn74G7JCAceiJY/V4t0/PlkxznhE8pjSZcePoF?= =?utf-8?q?dXyncWJRb4QjWkmvIB+x11TdQ9u5FxGfXTUDHs7lxjxkE/YihTPGRgbi07ZR5hp02?= =?utf-8?q?jCKRrBd+z/phwZShW91qT23w5dNJYnOP02yhpwY6dLwr/QOhGFeHwjSTD4gNgtXO5?= =?utf-8?q?OcccJcMDAz00aDTFqPmPKx+kTCRgHTVLgNuNMMEB8QEsY1aNNxleHjj20CwVYTdlS?= =?utf-8?q?95y89c8JG0BHAppv4yg1Y96FtM84HM0He+ceokDOvQzX3vAp3YuwBW9bfRQUGfAQ1?= =?utf-8?q?vupc/MFCgr5+NOsTjh1hTsQdM3Akvg82zySiCw0SQwscFIv/l4dR4ZVH0XF/hfz1Z?= =?utf-8?q?nW620P7NyTuNPVb4PmJiNux75bmhZiCJzhCt2FyKLS/KoKh03sggH79hrQ1hU5YBl?= =?utf-8?q?A6UQ+qgmMExuJ0BjxRhcK6ZbIAMjqtRSnFtRIiMVTC3YPGZCJ1wVOUlQrO/ZvqbwZ?= =?utf-8?q?bSUvs9CIZkrIY8CGQlo5qnCP8EiY4XUZb+9XSgL5orn9G85OQYrpAl9jjnrY+Q16l?= =?utf-8?q?OIZtQaFg7OjqHLnOA0aVzKru+LgWAXc2DHUUvavZnwNEypOS4wHe1aCvSQpbvjEPT?= =?utf-8?q?ltAIhyNbSQlGi4zhOsyX/7uacSHrsi+DUxKdWtXmkUOLhbW7nYw18QfWdA/5tnHK9?= =?utf-8?q?5lbBQBffMUWr8EETBy5LQAT7uJ1KSbLtHDZ6WCFEiYM84y8I5xUgQabg+I5EjNrdh?= =?utf-8?q?sZQksV8R0XXRYtnFR8kZKKfdMZXKZKXHWrjXY2XQZm44a9hSGnKOSwjes7DQqGeZC?= =?utf-8?q?ew+v9fiY88UeNbVUf4kD4tQPhUUd+PFSAx9gBx4h0VJBe4RBJRSiqyQOBmk2XAeuh?= =?utf-8?q?yq8I/KCgyKRpjEjCHgK3pyYWZlYHbzSAWzggfFDjKglbh5erO9y6ta0iozOZpwQos?= =?utf-8?q?SZxKUF0a1TDskvNziyplxGorcuZoN3vbw7nbSQcnpCp+QohHiS5QsGT7KHOnOhdvO?= =?utf-8?q?Rfgs0Bf5k1yaIqFLR7yZVwmGgcd6vkTQaSOIUghoaci3BTiiPnNX2Qu3C22eQOEHG?= =?utf-8?q?nQ1g9XHbXphriqfYyqqayVBLcCqRR0Q/os5vTBmeCr+r/gVX4+2H8d9RSgnjfNg2c?= =?utf-8?q?r1SypEVLM0pvHaW8Vs8RTc+UUzh6muQbB0a0vKz37DuutfQdLRXUrjzQb8VLl5Gbu?= =?utf-8?q?TfYP5AHXEVfVgq1PFUTouRw6WEaCednrQeyBQ85oP9GHkMhb4MwGkF911oFNlzH4M?= =?utf-8?q?04IxMM2YGvjYyia7HjdN5bA3FiZ+tuxxWygLvm+YZ6EsJNo0b7BgNcYiYero2ez8z?= =?utf-8?q?D5M6fQaPvcXHsvsJtkM9kcOaH1v/uIA1ZY8q4Gqtnwkr+zzWeqJ/blAlM3yadEztJ?= =?utf-8?q?Qcz9TfCIh7ak?= X-OriginatorOrg: oss.nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: d05c2861-10d0-4168-dd45-08dcef5a961c X-MS-Exchange-CrossTenant-AuthSource: PAXPR04MB8459.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 Oct 2024 09:52:32.5843 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: BlJNxB6c06PDt+XxCWxMk4Bni+t3v45/nI+hxnTJdrus3UNqvfrwDcz4hEAloQ0a5UfY8IEx0MSc0Sb+sWYVcw== X-MS-Exchange-Transport-CrossTenantHeadersStamped: DBAPR04MB7285 From: Peng Fan Back-to-back LPCG writes can be ignored by the LPCG register due to a HW bug. The writes need to be separated by at least 4 cycles of the gated clock. See https://www.nxp.com.cn/docs/en/errata/IMX8_1N94W.pdf The workaround is implemented as follows: 1. For clocks running greater than or equal to 24MHz, a read followed by the write will provide sufficient delay. 2. For clocks running below 24MHz, add a delay of 4 clock cylces after the write to the LPCG register. Fixes: 2f77296d3df9 ("clk: imx: add lpcg clock support") Signed-off-by: Peng Fan --- drivers/clk/imx/clk-lpcg-scu.c | 35 +++++++++++++++++++++++++++++++---- 1 file changed, 31 insertions(+), 4 deletions(-) diff --git a/drivers/clk/imx/clk-lpcg-scu.c b/drivers/clk/imx/clk-lpcg-scu.c index dd5abd09f3e206a5073767561b517d5b3320b28c..cd42190233662c66f2c354f0a2eee3a2531eeb3a 100644 --- a/drivers/clk/imx/clk-lpcg-scu.c +++ b/drivers/clk/imx/clk-lpcg-scu.c @@ -6,10 +6,12 @@ #include #include +#include #include #include #include #include +#include #include "clk-scu.h" @@ -41,6 +43,31 @@ struct clk_lpcg_scu { #define to_clk_lpcg_scu(_hw) container_of(_hw, struct clk_lpcg_scu, hw) +/* e10858 -LPCG clock gating register synchronization errata */ +static void lpcg_e10858_writel(unsigned long rate, void __iomem *reg, u32 val) +{ + u32 reg1; + + writel(val, reg); + + if (rate >= 24 * HZ_PER_MHZ || rate == 0) { + /* + * The time taken to access the LPCG registers from the AP core + * through the interconnect is longer than the minimum delay + * of 4 clock cycles required by the errata. + * Adding a readl will provide sufficient delay to prevent + * back-to-back writes. + */ + reg1 = readl(reg); + } else { + /* + * For clocks running below 24MHz, wait a minimum of + * 4 clock cycles. + */ + ndelay(4 * (DIV_ROUND_UP(1000 * HZ_PER_MHZ, rate))); + } +} + static int clk_lpcg_scu_enable(struct clk_hw *hw) { struct clk_lpcg_scu *clk = to_clk_lpcg_scu(hw); @@ -57,7 +84,8 @@ static int clk_lpcg_scu_enable(struct clk_hw *hw) val |= CLK_GATE_SCU_LPCG_HW_SEL; reg |= val << clk->bit_idx; - writel(reg, clk->reg); + + lpcg_e10858_writel(clk_hw_get_rate(hw), clk->reg, reg); spin_unlock_irqrestore(&imx_lpcg_scu_lock, flags); @@ -74,7 +102,7 @@ static void clk_lpcg_scu_disable(struct clk_hw *hw) reg = readl_relaxed(clk->reg); reg &= ~(CLK_GATE_SCU_LPCG_MASK << clk->bit_idx); - writel(reg, clk->reg); + lpcg_e10858_writel(clk_hw_get_rate(hw), clk->reg, reg); spin_unlock_irqrestore(&imx_lpcg_scu_lock, flags); } @@ -149,9 +177,8 @@ static int __maybe_unused imx_clk_lpcg_scu_resume(struct device *dev) * FIXME: Sometimes writes don't work unless the CPU issues * them twice */ - - writel(clk->state, clk->reg); writel(clk->state, clk->reg); + lpcg_e10858_writel(0, clk->reg, clk->state); dev_dbg(dev, "restore lpcg state 0x%x\n", clk->state); return 0;