| Message ID | 20241203-imx95_lut-v7-2-d0cd6293225e@nxp.com (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | PCI: add enabe(disable)_device() hook for bridge | expand |
On Tue, Dec 03, 2024 at 06:27:16PM -0500, Frank Li wrote: > For the i.MX95, configuration of a LUT is necessary to convert Bus Device > Function (BDF) to stream IDs, which are utilized by both IOMMU and ITS. > This involves examining the msi-map and smmu-map to ensure consistent This involves checking msi-map and iommu-map device tree properties to... > mapping of PCI BDF to the same stream IDs. Subsequently, LUT-related > registers are configured. In the absence of an msi-map, the built-in MSI > controller is utilized as a fallback. > > Register a PCI bus callback function to handle enable_device() and > disable_device() operations, setting up the LUT whenever a new PCI device > is enabled. > > Acked-by: Richard Zhu <hongxing.zhu@nxp.com> > Signed-off-by: Frank Li <Frank.Li@nxp.com> > --- > Change from v5 to v6 > - change comment rid to RID > - some mini change according to mani's feedback > > Change from v4 to v5 > - rework commt message > - add comment for mutex > - s/reqid/rid/ > - keep only one loop when enable lut > - add warning when try to add duplicate rid > - Replace hardcode 0xffff with IMX95_PE0_LUT_MASK > - Fix some error message > > Change from v3 to v4 > - Check target value at of_map_id(). > - of_node_put() for target. > - add case for msi-map exist, but rid entry is not exist. > > Change from v2 to v3 > - Use the "target" argument of of_map_id() > - Check if rid already in lut table when enable device > > change from v1 to v2 > - set callback to pci_host_bridge instead pci->ops. > --- > drivers/pci/controller/dwc/pci-imx6.c | 183 +++++++++++++++++++++++++++++++++- > 1 file changed, 182 insertions(+), 1 deletion(-) > > diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c > index c8d5c90aa4d45..ac5caa7b05075 100644 > --- a/drivers/pci/controller/dwc/pci-imx6.c > +++ b/drivers/pci/controller/dwc/pci-imx6.c > @@ -55,6 +55,22 @@ > #define IMX95_PE0_GEN_CTRL_3 0x1058 > #define IMX95_PCIE_LTSSM_EN BIT(0) > > +#define IMX95_PE0_LUT_ACSCTRL 0x1008 > +#define IMX95_PEO_LUT_RWA BIT(16) > +#define IMX95_PE0_LUT_ENLOC GENMASK(4, 0) > + > +#define IMX95_PE0_LUT_DATA1 0x100c > +#define IMX95_PE0_LUT_VLD BIT(31) > +#define IMX95_PE0_LUT_DAC_ID GENMASK(10, 8) > +#define IMX95_PE0_LUT_STREAM_ID GENMASK(5, 0) > + > +#define IMX95_PE0_LUT_DATA2 0x1010 > +#define IMX95_PE0_LUT_REQID GENMASK(31, 16) > +#define IMX95_PE0_LUT_MASK GENMASK(15, 0) > + > +#define IMX95_SID_MASK GENMASK(5, 0) > +#define IMX95_MAX_LUT 32 > + > #define to_imx_pcie(x) dev_get_drvdata((x)->dev) > > enum imx_pcie_variants { > @@ -87,6 +103,7 @@ enum imx_pcie_variants { > * workaround suspend resume on some devices which are affected by this errata. > */ > #define IMX_PCIE_FLAG_BROKEN_SUSPEND BIT(9) > +#define IMX_PCIE_FLAG_HAS_LUT BIT(10) > > #define imx_check_flag(pci, val) (pci->drvdata->flags & val) > > @@ -139,6 +156,9 @@ struct imx_pcie { > struct device *pd_pcie_phy; > struct phy *phy; > const struct imx_pcie_drvdata *drvdata; > + > + /* Ensure that only one device's LUT is configured at any given time */ > + struct mutex lock; > }; > > /* Parameters for the waiting for PCIe PHY PLL to lock on i.MX7 */ > @@ -930,6 +950,159 @@ static void imx_pcie_stop_link(struct dw_pcie *pci) > imx_pcie_ltssm_disable(dev); > } > > +static int imx_pcie_add_lut(struct imx_pcie *imx_pcie, u16 rid, u8 sid) > +{ > + struct dw_pcie *pci = imx_pcie->pci; > + struct device *dev = pci->dev; > + u32 data1, data2; > + int free = -1; > + int i; > + > + if (sid >= 64) { > + dev_err(dev, "Invalid SID for index %d\n", sid); > + return -EINVAL; > + } > + > + guard(mutex)(&imx_pcie->lock); > + > + /* > + * Iterate through all LUT entries to check for duplicate RID and > + * identify the first available entry. Configure this available entry > + * immediately after verification to avoid rescanning it. > + */ > + for (i = 0; i < IMX95_MAX_LUT; i++) { > + regmap_write(imx_pcie->iomuxc_gpr, IMX95_PE0_LUT_ACSCTRL, IMX95_PEO_LUT_RWA | i); > + regmap_read(imx_pcie->iomuxc_gpr, IMX95_PE0_LUT_DATA1, &data1); > + > + if (!(data1 & IMX95_PE0_LUT_VLD)) { > + if (free < 0) > + free = i; > + continue; > + } > + > + regmap_read(imx_pcie->iomuxc_gpr, IMX95_PE0_LUT_DATA2, &data2); > + > + /* Do not add duplicate RID */ > + if (rid == FIELD_GET(IMX95_PE0_LUT_REQID, data2)) { > + dev_warn(dev, "Existing LUT entry available for RID (%d)", rid); > + return 0; > + } > + } > + > + if (free < 0) { > + dev_err(dev, "LUT entry is not available\n"); > + return -ENOSPC; > + } > + > + data1 = FIELD_PREP(IMX95_PE0_LUT_DAC_ID, 0); > + data1 |= FIELD_PREP(IMX95_PE0_LUT_STREAM_ID, sid); > + data1 |= IMX95_PE0_LUT_VLD; > + regmap_write(imx_pcie->iomuxc_gpr, IMX95_PE0_LUT_DATA1, data1); > + > + data2 = IMX95_PE0_LUT_MASK; /* Match all bits of RID */ > + data2 |= FIELD_PREP(IMX95_PE0_LUT_REQID, rid); > + regmap_write(imx_pcie->iomuxc_gpr, IMX95_PE0_LUT_DATA2, data2); > + > + regmap_write(imx_pcie->iomuxc_gpr, IMX95_PE0_LUT_ACSCTRL, free); > + > + return 0; > +} > + > +static void imx_pcie_remove_lut(struct imx_pcie *imx_pcie, u16 rid) > +{ > + u32 data2; > + int i; > + > + guard(mutex)(&imx_pcie->lock); > + > + for (i = 0; i < IMX95_MAX_LUT; i++) { > + regmap_write(imx_pcie->iomuxc_gpr, IMX95_PE0_LUT_ACSCTRL, IMX95_PEO_LUT_RWA | i); > + regmap_read(imx_pcie->iomuxc_gpr, IMX95_PE0_LUT_DATA2, &data2); > + if (FIELD_GET(IMX95_PE0_LUT_REQID, data2) == rid) { > + regmap_write(imx_pcie->iomuxc_gpr, IMX95_PE0_LUT_DATA1, 0); > + regmap_write(imx_pcie->iomuxc_gpr, IMX95_PE0_LUT_DATA2, 0); > + regmap_write(imx_pcie->iomuxc_gpr, IMX95_PE0_LUT_ACSCTRL, i); > + > + break; > + } > + } > +} > + > +static int imx_pcie_enable_device(struct pci_host_bridge *bridge, struct pci_dev *pdev) > +{ > + struct imx_pcie *imx_pcie = to_imx_pcie(to_dw_pcie_from_pp(bridge->sysdata)); > + u32 sid_i, sid_m, rid = pci_dev_id(pdev); > + struct device_node *target; > + struct device *dev; > + int err_i, err_m; > + > + dev = imx_pcie->pci->dev; > + > + target = NULL; > + err_i = of_map_id(dev->of_node, rid, "iommu-map", "iommu-map-mask", &target, &sid_i); > + if (target) > + of_node_put(target); > + else > + err_i = -EINVAL; Why ? If target == NULL err_i is already set to a negative value ? > + > + target = NULL; > + err_m = of_map_id(dev->of_node, rid, "msi-map", "msi-map-mask", &target, &sid_m); > + > + /* > + * Return failure if msi-map exist and no entry for RID because dwc common > + * driver will skip setting up built-in MSI controller if msi-map existed. This is not ideal - to depend on the DWC common driver behaviour. > + * > + * err_m target > + * 0 NULL Return failure, function not work. > + * !0 NULL msi-map not exist, use built-in MSI. ^^^^ "function not work" does not mean anything, sorry. What is it meant to say ? !=0 > + * 0 !NULL Find one entry. > + * !0 !NULL Invalidate case. "Find one entry", "Invalidate case", I don't understand what they mean. !=0 !=NULL > + */ > + if (!err_m && !target) > + return -EINVAL; > + else if (target) > + of_node_put(target); /* Find entry for RID in msi-map */ > + > + /* > + * msi-map iommu-map > + * Y Y ITS + SMMU, require the same sid > + * Y N ITS > + * N Y DWC MSI Ctrl + SMMU > + * N N DWC MSI Ctrl > + */ > + if (!err_i && !err_m) > + if ((sid_i & IMX95_SID_MASK) != (sid_m & IMX95_SID_MASK)) { Here you mask sid_i > + dev_err(dev, "iommu-map and msi-map entries mismatch!\n"); > + return -EINVAL; > + } > + > + /* > + * Both iommu-map and msi-map not exist, use dwc built-in MSI > + * controller, do nothing here. > + */ > + if (err_i && err_m) > + return 0; > + > + if (!err_i) > + return imx_pcie_add_lut(imx_pcie, rid, sid_i); Here you don't ? Moreover - this would also cater for the case where (!err_i && !err_m) is true ? Probably cleaner to do: u32 sid; if (err_i && err_m) return 0; if (!err_i && !err_m) { if ((sid_i & IMX95_SID_MASK) != (sid_m & IMX95_SID_MASK)) { dev_err(dev, "iommu-map and msi-map entries mismatch!\n"); return -EINVAL; } } if (!err_i) sid = sid_i & IMX95_SID_MASK; else if (!err_m) sid = sid_m & IMX95_SID_MASK; return imx_pcie_add_lut(imx_pcie, rid, sid); > + else if (!err_m) > + /* > + * Hardware auto add 2 bits controller id ahead of stream ID, > + * so mask this 2bits to get stream ID. > + */ > + return imx_pcie_add_lut(imx_pcie, rid, sid_m & IMX95_SID_MASK); > + > + return 0; return 0; is dead code AFAICS. > +} > + > +static void imx_pcie_disable_device(struct pci_host_bridge *bridge, struct pci_dev *pdev) > +{ > + struct imx_pcie *imx_pcie; > + > + imx_pcie = to_imx_pcie(to_dw_pcie_from_pp(bridge->sysdata)); > + imx_pcie_remove_lut(imx_pcie, pci_dev_id(pdev)); > +} > + > static int imx_pcie_host_init(struct dw_pcie_rp *pp) > { > struct dw_pcie *pci = to_dw_pcie_from_pp(pp); > @@ -946,6 +1119,11 @@ static int imx_pcie_host_init(struct dw_pcie_rp *pp) > } > } > > + if (pp->bridge && imx_check_flag(imx_pcie, IMX_PCIE_FLAG_HAS_LUT)) { > + pp->bridge->enable_device = imx_pcie_enable_device; > + pp->bridge->disable_device = imx_pcie_disable_device; > + } > + > imx_pcie_assert_core_reset(imx_pcie); > > if (imx_pcie->drvdata->init_phy) > @@ -1330,6 +1508,8 @@ static int imx_pcie_probe(struct platform_device *pdev) > imx_pcie->pci = pci; > imx_pcie->drvdata = of_device_get_match_data(dev); > > + mutex_init(&imx_pcie->lock); > + > /* Find the PHY if one is defined, only imx7d uses it */ > np = of_parse_phandle(node, "fsl,imx7d-pcie-phy", 0); > if (np) { > @@ -1627,7 +1807,8 @@ static const struct imx_pcie_drvdata drvdata[] = { > }, > [IMX95] = { > .variant = IMX95, > - .flags = IMX_PCIE_FLAG_HAS_SERDES, > + .flags = IMX_PCIE_FLAG_HAS_SERDES | > + IMX_PCIE_FLAG_HAS_LUT, > .clk_names = imx8mq_clks, > .clks_cnt = ARRAY_SIZE(imx8mq_clks), > .ltssm_off = IMX95_PE0_GEN_CTRL_3, > > -- > 2.34.1 >
On Thu, Dec 05, 2024 at 11:25:07AM +0100, Lorenzo Pieralisi wrote: > On Tue, Dec 03, 2024 at 06:27:16PM -0500, Frank Li wrote: > > For the i.MX95, configuration of a LUT is necessary to convert Bus Device > > Function (BDF) to stream IDs, which are utilized by both IOMMU and ITS. > > This involves examining the msi-map and smmu-map to ensure consistent > > This involves checking msi-map and iommu-map device tree properties > to... > > > mapping of PCI BDF to the same stream IDs. Subsequently, LUT-related > > registers are configured. In the absence of an msi-map, the built-in MSI > > controller is utilized as a fallback. > > > > Register a PCI bus callback function to handle enable_device() and > > disable_device() operations, setting up the LUT whenever a new PCI device > > is enabled. > > > > Acked-by: Richard Zhu <hongxing.zhu@nxp.com> > > Signed-off-by: Frank Li <Frank.Li@nxp.com> > > --- > > Change from v5 to v6 > > - change comment rid to RID > > - some mini change according to mani's feedback > > > > Change from v4 to v5 > > - rework commt message > > - add comment for mutex > > - s/reqid/rid/ > > - keep only one loop when enable lut > > - add warning when try to add duplicate rid > > - Replace hardcode 0xffff with IMX95_PE0_LUT_MASK > > - Fix some error message > > > > Change from v3 to v4 > > - Check target value at of_map_id(). > > - of_node_put() for target. > > - add case for msi-map exist, but rid entry is not exist. > > > > Change from v2 to v3 > > - Use the "target" argument of of_map_id() > > - Check if rid already in lut table when enable device > > > > change from v1 to v2 > > - set callback to pci_host_bridge instead pci->ops. > > --- > > drivers/pci/controller/dwc/pci-imx6.c | 183 +++++++++++++++++++++++++++++++++- > > 1 file changed, 182 insertions(+), 1 deletion(-) > > > > diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c > > index c8d5c90aa4d45..ac5caa7b05075 100644 > > --- a/drivers/pci/controller/dwc/pci-imx6.c > > +++ b/drivers/pci/controller/dwc/pci-imx6.c > > @@ -55,6 +55,22 @@ > > #define IMX95_PE0_GEN_CTRL_3 0x1058 > > #define IMX95_PCIE_LTSSM_EN BIT(0) > > > > +#define IMX95_PE0_LUT_ACSCTRL 0x1008 > > +#define IMX95_PEO_LUT_RWA BIT(16) > > +#define IMX95_PE0_LUT_ENLOC GENMASK(4, 0) > > + > > +#define IMX95_PE0_LUT_DATA1 0x100c > > +#define IMX95_PE0_LUT_VLD BIT(31) > > +#define IMX95_PE0_LUT_DAC_ID GENMASK(10, 8) > > +#define IMX95_PE0_LUT_STREAM_ID GENMASK(5, 0) > > + > > +#define IMX95_PE0_LUT_DATA2 0x1010 > > +#define IMX95_PE0_LUT_REQID GENMASK(31, 16) > > +#define IMX95_PE0_LUT_MASK GENMASK(15, 0) > > + > > +#define IMX95_SID_MASK GENMASK(5, 0) > > +#define IMX95_MAX_LUT 32 > > + > > #define to_imx_pcie(x) dev_get_drvdata((x)->dev) > > > > enum imx_pcie_variants { > > @@ -87,6 +103,7 @@ enum imx_pcie_variants { > > * workaround suspend resume on some devices which are affected by this errata. > > */ > > #define IMX_PCIE_FLAG_BROKEN_SUSPEND BIT(9) > > +#define IMX_PCIE_FLAG_HAS_LUT BIT(10) > > > > #define imx_check_flag(pci, val) (pci->drvdata->flags & val) > > > > @@ -139,6 +156,9 @@ struct imx_pcie { > > struct device *pd_pcie_phy; > > struct phy *phy; > > const struct imx_pcie_drvdata *drvdata; > > + > > + /* Ensure that only one device's LUT is configured at any given time */ > > + struct mutex lock; > > }; > > > > /* Parameters for the waiting for PCIe PHY PLL to lock on i.MX7 */ > > @@ -930,6 +950,159 @@ static void imx_pcie_stop_link(struct dw_pcie *pci) > > imx_pcie_ltssm_disable(dev); > > } > > > > +static int imx_pcie_add_lut(struct imx_pcie *imx_pcie, u16 rid, u8 sid) > > +{ > > + struct dw_pcie *pci = imx_pcie->pci; > > + struct device *dev = pci->dev; > > + u32 data1, data2; > > + int free = -1; > > + int i; > > + > > + if (sid >= 64) { > > + dev_err(dev, "Invalid SID for index %d\n", sid); > > + return -EINVAL; > > + } > > + > > + guard(mutex)(&imx_pcie->lock); > > + > > + /* > > + * Iterate through all LUT entries to check for duplicate RID and > > + * identify the first available entry. Configure this available entry > > + * immediately after verification to avoid rescanning it. > > + */ > > + for (i = 0; i < IMX95_MAX_LUT; i++) { > > + regmap_write(imx_pcie->iomuxc_gpr, IMX95_PE0_LUT_ACSCTRL, IMX95_PEO_LUT_RWA | i); > > + regmap_read(imx_pcie->iomuxc_gpr, IMX95_PE0_LUT_DATA1, &data1); > > + > > + if (!(data1 & IMX95_PE0_LUT_VLD)) { > > + if (free < 0) > > + free = i; > > + continue; > > + } > > + > > + regmap_read(imx_pcie->iomuxc_gpr, IMX95_PE0_LUT_DATA2, &data2); > > + > > + /* Do not add duplicate RID */ > > + if (rid == FIELD_GET(IMX95_PE0_LUT_REQID, data2)) { > > + dev_warn(dev, "Existing LUT entry available for RID (%d)", rid); > > + return 0; > > + } > > + } > > + > > + if (free < 0) { > > + dev_err(dev, "LUT entry is not available\n"); > > + return -ENOSPC; > > + } > > + > > + data1 = FIELD_PREP(IMX95_PE0_LUT_DAC_ID, 0); > > + data1 |= FIELD_PREP(IMX95_PE0_LUT_STREAM_ID, sid); > > + data1 |= IMX95_PE0_LUT_VLD; > > + regmap_write(imx_pcie->iomuxc_gpr, IMX95_PE0_LUT_DATA1, data1); > > + > > + data2 = IMX95_PE0_LUT_MASK; /* Match all bits of RID */ > > + data2 |= FIELD_PREP(IMX95_PE0_LUT_REQID, rid); > > + regmap_write(imx_pcie->iomuxc_gpr, IMX95_PE0_LUT_DATA2, data2); > > + > > + regmap_write(imx_pcie->iomuxc_gpr, IMX95_PE0_LUT_ACSCTRL, free); > > + > > + return 0; > > +} > > + > > +static void imx_pcie_remove_lut(struct imx_pcie *imx_pcie, u16 rid) > > +{ > > + u32 data2; > > + int i; > > + > > + guard(mutex)(&imx_pcie->lock); > > + > > + for (i = 0; i < IMX95_MAX_LUT; i++) { > > + regmap_write(imx_pcie->iomuxc_gpr, IMX95_PE0_LUT_ACSCTRL, IMX95_PEO_LUT_RWA | i); > > + regmap_read(imx_pcie->iomuxc_gpr, IMX95_PE0_LUT_DATA2, &data2); > > + if (FIELD_GET(IMX95_PE0_LUT_REQID, data2) == rid) { > > + regmap_write(imx_pcie->iomuxc_gpr, IMX95_PE0_LUT_DATA1, 0); > > + regmap_write(imx_pcie->iomuxc_gpr, IMX95_PE0_LUT_DATA2, 0); > > + regmap_write(imx_pcie->iomuxc_gpr, IMX95_PE0_LUT_ACSCTRL, i); > > + > > + break; > > + } > > + } > > +} > > + > > +static int imx_pcie_enable_device(struct pci_host_bridge *bridge, struct pci_dev *pdev) > > +{ > > + struct imx_pcie *imx_pcie = to_imx_pcie(to_dw_pcie_from_pp(bridge->sysdata)); > > + u32 sid_i, sid_m, rid = pci_dev_id(pdev); > > + struct device_node *target; > > + struct device *dev; > > + int err_i, err_m; > > + > > + dev = imx_pcie->pci->dev; > > + > > + target = NULL; > > + err_i = of_map_id(dev->of_node, rid, "iommu-map", "iommu-map-mask", &target, &sid_i); > > + if (target) > > + of_node_put(target); > > + else > > + err_i = -EINVAL; > > Why ? If target == NULL err_i is already set to a negative value ? When no "iommu-map" exist, target == NULL, but err_i is 0. See below err_m table. > > > + > > + target = NULL; > > + err_m = of_map_id(dev->of_node, rid, "msi-map", "msi-map-mask", &target, &sid_m); > > + > > + /* > > + * Return failure if msi-map exist and no entry for RID because dwc common > > + * driver will skip setting up built-in MSI controller if msi-map existed. > > This is not ideal - to depend on the DWC common driver behaviour. > > > + * > > + * err_m target > > + * 0 NULL Return failure, function not work. > > + * !0 NULL msi-map not exist, use built-in MSI. > ^^^^ > "function not work" does not mean anything, sorry. What is it meant to > say ? RID is exeed what msi-map'r ranges for example RID MSI stream ID size <0x100, &its, 0x8, 0x1> If RID is 0x101, err_m is 0, target is NULL. sid_m will be 0x101, it is wrong, because max streamID width is 5bits. So it should return failure for this case. > > !=0 > > > + * 0 !NULL Find one entry. > > + * !0 !NULL Invalidate case. > > "Find one entry", "Invalidate case", I don't understand what they mean. Find one entry means get one streamID, as above example, RID = 0x100, sid will be 0x8. Invalidate case means never happen, this case doesn't exist. > > !=0 !=NULL > > > + */ > > + if (!err_m && !target) > > + return -EINVAL; > > + else if (target) > > + of_node_put(target); /* Find entry for RID in msi-map */ > > + > > + /* > > + * msi-map iommu-map > > + * Y Y ITS + SMMU, require the same sid > > + * Y N ITS > > + * N Y DWC MSI Ctrl + SMMU > > + * N N DWC MSI Ctrl > > + */ > > + if (!err_i && !err_m) > > + if ((sid_i & IMX95_SID_MASK) != (sid_m & IMX95_SID_MASK)) { > > Here you mask sid_i > > > + dev_err(dev, "iommu-map and msi-map entries mismatch!\n"); > > + return -EINVAL; > > + } > > + > > + /* > > + * Both iommu-map and msi-map not exist, use dwc built-in MSI > > + * controller, do nothing here. > > + */ > > + if (err_i && err_m) > > + return 0; > > + > > + if (!err_i) > > + return imx_pcie_add_lut(imx_pcie, rid, sid_i); > > Here you don't ? Okay, only need mask sid_m. > > Moreover - this would also cater for the case where (!err_i && !err_m) is > true ? > > Probably cleaner to do: > u32 sid; > > if (err_i && err_m) > return 0; > > if (!err_i && !err_m) { > if ((sid_i & IMX95_SID_MASK) != (sid_m & IMX95_SID_MASK)) { > dev_err(dev, "iommu-map and msi-map entries mismatch!\n"); > return -EINVAL; > } > } > > if (!err_i) > sid = sid_i & IMX95_SID_MASK; > else if (!err_m) > sid = sid_m & IMX95_SID_MASK; > > return imx_pcie_add_lut(imx_pcie, rid, sid); Okay. > > + else if (!err_m) > > + /* > > + * Hardware auto add 2 bits controller id ahead of stream ID, > > + * so mask this 2bits to get stream ID. > > + */ > > + return imx_pcie_add_lut(imx_pcie, rid, sid_m & IMX95_SID_MASK); > > + > > + return 0; > > return 0; is dead code AFAICS. > > > +} > > + > > +static void imx_pcie_disable_device(struct pci_host_bridge *bridge, struct pci_dev *pdev) > > +{ > > + struct imx_pcie *imx_pcie; > > + > > + imx_pcie = to_imx_pcie(to_dw_pcie_from_pp(bridge->sysdata)); > > + imx_pcie_remove_lut(imx_pcie, pci_dev_id(pdev)); > > +} > > + > > static int imx_pcie_host_init(struct dw_pcie_rp *pp) > > { > > struct dw_pcie *pci = to_dw_pcie_from_pp(pp); > > @@ -946,6 +1119,11 @@ static int imx_pcie_host_init(struct dw_pcie_rp *pp) > > } > > } > > > > + if (pp->bridge && imx_check_flag(imx_pcie, IMX_PCIE_FLAG_HAS_LUT)) { > > + pp->bridge->enable_device = imx_pcie_enable_device; > > + pp->bridge->disable_device = imx_pcie_disable_device; > > + } > > + > > imx_pcie_assert_core_reset(imx_pcie); > > > > if (imx_pcie->drvdata->init_phy) > > @@ -1330,6 +1508,8 @@ static int imx_pcie_probe(struct platform_device *pdev) > > imx_pcie->pci = pci; > > imx_pcie->drvdata = of_device_get_match_data(dev); > > > > + mutex_init(&imx_pcie->lock); > > + > > /* Find the PHY if one is defined, only imx7d uses it */ > > np = of_parse_phandle(node, "fsl,imx7d-pcie-phy", 0); > > if (np) { > > @@ -1627,7 +1807,8 @@ static const struct imx_pcie_drvdata drvdata[] = { > > }, > > [IMX95] = { > > .variant = IMX95, > > - .flags = IMX_PCIE_FLAG_HAS_SERDES, > > + .flags = IMX_PCIE_FLAG_HAS_SERDES | > > + IMX_PCIE_FLAG_HAS_LUT, > > .clk_names = imx8mq_clks, > > .clks_cnt = ARRAY_SIZE(imx8mq_clks), > > .ltssm_off = IMX95_PE0_GEN_CTRL_3, > > > > -- > > 2.34.1 > >
diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c index c8d5c90aa4d45..ac5caa7b05075 100644 --- a/drivers/pci/controller/dwc/pci-imx6.c +++ b/drivers/pci/controller/dwc/pci-imx6.c @@ -55,6 +55,22 @@ #define IMX95_PE0_GEN_CTRL_3 0x1058 #define IMX95_PCIE_LTSSM_EN BIT(0) +#define IMX95_PE0_LUT_ACSCTRL 0x1008 +#define IMX95_PEO_LUT_RWA BIT(16) +#define IMX95_PE0_LUT_ENLOC GENMASK(4, 0) + +#define IMX95_PE0_LUT_DATA1 0x100c +#define IMX95_PE0_LUT_VLD BIT(31) +#define IMX95_PE0_LUT_DAC_ID GENMASK(10, 8) +#define IMX95_PE0_LUT_STREAM_ID GENMASK(5, 0) + +#define IMX95_PE0_LUT_DATA2 0x1010 +#define IMX95_PE0_LUT_REQID GENMASK(31, 16) +#define IMX95_PE0_LUT_MASK GENMASK(15, 0) + +#define IMX95_SID_MASK GENMASK(5, 0) +#define IMX95_MAX_LUT 32 + #define to_imx_pcie(x) dev_get_drvdata((x)->dev) enum imx_pcie_variants { @@ -87,6 +103,7 @@ enum imx_pcie_variants { * workaround suspend resume on some devices which are affected by this errata. */ #define IMX_PCIE_FLAG_BROKEN_SUSPEND BIT(9) +#define IMX_PCIE_FLAG_HAS_LUT BIT(10) #define imx_check_flag(pci, val) (pci->drvdata->flags & val) @@ -139,6 +156,9 @@ struct imx_pcie { struct device *pd_pcie_phy; struct phy *phy; const struct imx_pcie_drvdata *drvdata; + + /* Ensure that only one device's LUT is configured at any given time */ + struct mutex lock; }; /* Parameters for the waiting for PCIe PHY PLL to lock on i.MX7 */ @@ -930,6 +950,159 @@ static void imx_pcie_stop_link(struct dw_pcie *pci) imx_pcie_ltssm_disable(dev); } +static int imx_pcie_add_lut(struct imx_pcie *imx_pcie, u16 rid, u8 sid) +{ + struct dw_pcie *pci = imx_pcie->pci; + struct device *dev = pci->dev; + u32 data1, data2; + int free = -1; + int i; + + if (sid >= 64) { + dev_err(dev, "Invalid SID for index %d\n", sid); + return -EINVAL; + } + + guard(mutex)(&imx_pcie->lock); + + /* + * Iterate through all LUT entries to check for duplicate RID and + * identify the first available entry. Configure this available entry + * immediately after verification to avoid rescanning it. + */ + for (i = 0; i < IMX95_MAX_LUT; i++) { + regmap_write(imx_pcie->iomuxc_gpr, IMX95_PE0_LUT_ACSCTRL, IMX95_PEO_LUT_RWA | i); + regmap_read(imx_pcie->iomuxc_gpr, IMX95_PE0_LUT_DATA1, &data1); + + if (!(data1 & IMX95_PE0_LUT_VLD)) { + if (free < 0) + free = i; + continue; + } + + regmap_read(imx_pcie->iomuxc_gpr, IMX95_PE0_LUT_DATA2, &data2); + + /* Do not add duplicate RID */ + if (rid == FIELD_GET(IMX95_PE0_LUT_REQID, data2)) { + dev_warn(dev, "Existing LUT entry available for RID (%d)", rid); + return 0; + } + } + + if (free < 0) { + dev_err(dev, "LUT entry is not available\n"); + return -ENOSPC; + } + + data1 = FIELD_PREP(IMX95_PE0_LUT_DAC_ID, 0); + data1 |= FIELD_PREP(IMX95_PE0_LUT_STREAM_ID, sid); + data1 |= IMX95_PE0_LUT_VLD; + regmap_write(imx_pcie->iomuxc_gpr, IMX95_PE0_LUT_DATA1, data1); + + data2 = IMX95_PE0_LUT_MASK; /* Match all bits of RID */ + data2 |= FIELD_PREP(IMX95_PE0_LUT_REQID, rid); + regmap_write(imx_pcie->iomuxc_gpr, IMX95_PE0_LUT_DATA2, data2); + + regmap_write(imx_pcie->iomuxc_gpr, IMX95_PE0_LUT_ACSCTRL, free); + + return 0; +} + +static void imx_pcie_remove_lut(struct imx_pcie *imx_pcie, u16 rid) +{ + u32 data2; + int i; + + guard(mutex)(&imx_pcie->lock); + + for (i = 0; i < IMX95_MAX_LUT; i++) { + regmap_write(imx_pcie->iomuxc_gpr, IMX95_PE0_LUT_ACSCTRL, IMX95_PEO_LUT_RWA | i); + regmap_read(imx_pcie->iomuxc_gpr, IMX95_PE0_LUT_DATA2, &data2); + if (FIELD_GET(IMX95_PE0_LUT_REQID, data2) == rid) { + regmap_write(imx_pcie->iomuxc_gpr, IMX95_PE0_LUT_DATA1, 0); + regmap_write(imx_pcie->iomuxc_gpr, IMX95_PE0_LUT_DATA2, 0); + regmap_write(imx_pcie->iomuxc_gpr, IMX95_PE0_LUT_ACSCTRL, i); + + break; + } + } +} + +static int imx_pcie_enable_device(struct pci_host_bridge *bridge, struct pci_dev *pdev) +{ + struct imx_pcie *imx_pcie = to_imx_pcie(to_dw_pcie_from_pp(bridge->sysdata)); + u32 sid_i, sid_m, rid = pci_dev_id(pdev); + struct device_node *target; + struct device *dev; + int err_i, err_m; + + dev = imx_pcie->pci->dev; + + target = NULL; + err_i = of_map_id(dev->of_node, rid, "iommu-map", "iommu-map-mask", &target, &sid_i); + if (target) + of_node_put(target); + else + err_i = -EINVAL; + + target = NULL; + err_m = of_map_id(dev->of_node, rid, "msi-map", "msi-map-mask", &target, &sid_m); + + /* + * Return failure if msi-map exist and no entry for RID because dwc common + * driver will skip setting up built-in MSI controller if msi-map existed. + * + * err_m target + * 0 NULL Return failure, function not work. + * !0 NULL msi-map not exist, use built-in MSI. + * 0 !NULL Find one entry. + * !0 !NULL Invalidate case. + */ + if (!err_m && !target) + return -EINVAL; + else if (target) + of_node_put(target); /* Find entry for RID in msi-map */ + + /* + * msi-map iommu-map + * Y Y ITS + SMMU, require the same sid + * Y N ITS + * N Y DWC MSI Ctrl + SMMU + * N N DWC MSI Ctrl + */ + if (!err_i && !err_m) + if ((sid_i & IMX95_SID_MASK) != (sid_m & IMX95_SID_MASK)) { + dev_err(dev, "iommu-map and msi-map entries mismatch!\n"); + return -EINVAL; + } + + /* + * Both iommu-map and msi-map not exist, use dwc built-in MSI + * controller, do nothing here. + */ + if (err_i && err_m) + return 0; + + if (!err_i) + return imx_pcie_add_lut(imx_pcie, rid, sid_i); + else if (!err_m) + /* + * Hardware auto add 2 bits controller id ahead of stream ID, + * so mask this 2bits to get stream ID. + */ + return imx_pcie_add_lut(imx_pcie, rid, sid_m & IMX95_SID_MASK); + + return 0; +} + +static void imx_pcie_disable_device(struct pci_host_bridge *bridge, struct pci_dev *pdev) +{ + struct imx_pcie *imx_pcie; + + imx_pcie = to_imx_pcie(to_dw_pcie_from_pp(bridge->sysdata)); + imx_pcie_remove_lut(imx_pcie, pci_dev_id(pdev)); +} + static int imx_pcie_host_init(struct dw_pcie_rp *pp) { struct dw_pcie *pci = to_dw_pcie_from_pp(pp); @@ -946,6 +1119,11 @@ static int imx_pcie_host_init(struct dw_pcie_rp *pp) } } + if (pp->bridge && imx_check_flag(imx_pcie, IMX_PCIE_FLAG_HAS_LUT)) { + pp->bridge->enable_device = imx_pcie_enable_device; + pp->bridge->disable_device = imx_pcie_disable_device; + } + imx_pcie_assert_core_reset(imx_pcie); if (imx_pcie->drvdata->init_phy) @@ -1330,6 +1508,8 @@ static int imx_pcie_probe(struct platform_device *pdev) imx_pcie->pci = pci; imx_pcie->drvdata = of_device_get_match_data(dev); + mutex_init(&imx_pcie->lock); + /* Find the PHY if one is defined, only imx7d uses it */ np = of_parse_phandle(node, "fsl,imx7d-pcie-phy", 0); if (np) { @@ -1627,7 +1807,8 @@ static const struct imx_pcie_drvdata drvdata[] = { }, [IMX95] = { .variant = IMX95, - .flags = IMX_PCIE_FLAG_HAS_SERDES, + .flags = IMX_PCIE_FLAG_HAS_SERDES | + IMX_PCIE_FLAG_HAS_LUT, .clk_names = imx8mq_clks, .clks_cnt = ARRAY_SIZE(imx8mq_clks), .ltssm_off = IMX95_PE0_GEN_CTRL_3,