From patchwork Fri Dec 6 07:09:53 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ciprian Costea X-Patchwork-Id: 13896557 Received: from EUR05-DB8-obe.outbound.protection.outlook.com (mail-db8eur05on2071.outbound.protection.outlook.com [40.107.20.71]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 661381DB551 for ; Fri, 6 Dec 2024 07:10:10 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.107.20.71 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733469013; cv=fail; b=Y4NXjFLzNSaTJ8YuOfPqqLCrLy2EYa+JlTsSLIUScQieoS3R3iHOsoeC4TvsTwxTtLvmq7E46xx48e62n20ShTKWhxkJuLNcXUoDd+vnqlPKaV5EtoKBOwyTZCc0pm21OoxGdKsBdhUKmB5V47azs+yY2ln5v6aFJSWu1KyfkNc= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733469013; c=relaxed/simple; bh=XyLduXwCdZxgo1D/t8dE9wvbrqHrx/v6TzeU1S6S/ts=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: Content-Type:MIME-Version; b=rVR+KUyoF1cZXb00QWA5ljXHXC0Zr+VNowxh3hU/CeaUURcb4n27/EGeLW5M3XH63MsigE2DF6KmWHOY2TYfZLCFcLLn6/3ue8K0dJy9Yo4KKtKMDRda+S+Nl5nULcZLQscrrJdCpOVOo8R5pRuQyGH+9dtMX7Kd7bGvLslxxYQ= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=oss.nxp.com; spf=pass smtp.mailfrom=oss.nxp.com; dkim=pass (2048-bit key) header.d=NXP1.onmicrosoft.com header.i=@NXP1.onmicrosoft.com header.b=rBJ2C3zB; arc=fail smtp.client-ip=40.107.20.71 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=oss.nxp.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.nxp.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=NXP1.onmicrosoft.com header.i=@NXP1.onmicrosoft.com header.b="rBJ2C3zB" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=sXBgY3qjmy3UODaM21riBhY5ZGcaLrk2ce/xjyGbKTf08Ir5kfccSlT5XtxF3FTOxMIOSuqcnlh9Q5+zqN/If2lbNP1S+TE4MTHE0ptt3AIwcraDmtxzLWczH8tVSy/l/GIk5cMRsX0okmzQB2RkiQ1Lo0FU8+EknAhvpJVhmda20Es6hBFPfmKnCnwGTar2ofvQftiUK7mW8MP6u3OSzDsJRMBumg94NsjEpnG9FPqfXt/bKoq3Pz5XYylm8bYSJZ34gGS6J/djDs+0dEuQFNCFj7joMF1PF+VCOFezPe5zJijVcs5g7D1U3OjCQV1hrj5gP+z2pNsZYj/vlyvV4w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=apYN15YTsL9Z97bWBv6JWjkGZMW4yQx4OhCXAAfPrOw=; b=yc2olaNPe8mFTvTj/0z6S+y/u5qiiRCtJ5jIjoL4NiE7fOOSd+/1Ceyd11rAB52ZEg2OwWp8iSUn/cQYkNTlMesFxy5H0eookTTTYrzZ/klinz7oHFgU5Uq/Ac67dJ41pyP7p5vMJCYNErS1iO/ncGklEytv2X+uQp00JD4IMtBZyv3awCFIi/RUQH+jTn0+eEDHQeCF2466DAgb16lz0KVqbvC5GvhmYM6Do9vBuhyskFFPj6GJwrJTV7iQbXJ9x2896CkhaQGB08kmYmy5MZ1WvuqiRSj0E/MOBAzHlz6BteCNPinhkirECS3AarI/PkL8VAU177QFSB+Sx6PhEA== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=oss.nxp.com; dmarc=pass action=none header.from=oss.nxp.com; dkim=pass header.d=oss.nxp.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=NXP1.onmicrosoft.com; s=selector1-NXP1-onmicrosoft-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=apYN15YTsL9Z97bWBv6JWjkGZMW4yQx4OhCXAAfPrOw=; b=rBJ2C3zB9b2mCHvJOsOsqBeFkTQBOw0y1TaXG+Ctg+tNKDNHl4PW+3NFJtd0yrlyioOTJeIMSfAuSJQrJdxL7Qdonp3sAOrC15RWTlmWVfI8Cn0j0+wDqaMpJfJt7UyQhzvOPFAmChC+UO2mPgDWxUCwprsnWD1uAwg7oftyifB+nBqiZHw22TOzZJJ5iIKIAWr1mcH87fIXxJ8/zdYa1vIxQ+L4do4JwNJ9ldBXMLiXAvh7+NgIA0NGwgDnIQDLyK5uyi7Pzd76SNSaa3ABmiZbWnfp2IgXcS5/ZBRZBTvZUGAlGjjt5tbxY6NCNi0y57Tld/qziPio7s43oDZhTA== Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=oss.nxp.com; Received: from DU0PR04MB9251.eurprd04.prod.outlook.com (2603:10a6:10:352::15) by DB9PR04MB9889.eurprd04.prod.outlook.com (2603:10a6:10:4ef::22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8230.10; Fri, 6 Dec 2024 07:10:03 +0000 Received: from DU0PR04MB9251.eurprd04.prod.outlook.com ([fe80::708f:69ee:15df:6ebd]) by DU0PR04MB9251.eurprd04.prod.outlook.com ([fe80::708f:69ee:15df:6ebd%6]) with mapi id 15.20.8207.017; Fri, 6 Dec 2024 07:10:03 +0000 From: Ciprian Costea To: Alexandre Belloni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Catalin Marinas , Will Deacon Cc: linux-rtc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, NXP S32 Linux , imx@lists.linux.dev, Christophe Lizzi , Alberto Ruiz , Enric Balletbo , Ciprian Marian Costea , Bogdan Hamciuc , Ghennadi Procopciuc Subject: [PATCH v6 2/4] rtc: s32g: add NXP S32G2/S32G3 SoC support Date: Fri, 6 Dec 2024 09:09:53 +0200 Message-ID: <20241206070955.1503412-3-ciprianmarian.costea@oss.nxp.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241206070955.1503412-1-ciprianmarian.costea@oss.nxp.com> References: <20241206070955.1503412-1-ciprianmarian.costea@oss.nxp.com> X-ClientProxiedBy: AM0PR06CA0080.eurprd06.prod.outlook.com (2603:10a6:208:fa::21) To DU0PR04MB9251.eurprd04.prod.outlook.com (2603:10a6:10:352::15) Precedence: bulk X-Mailing-List: imx@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DU0PR04MB9251:EE_|DB9PR04MB9889:EE_ X-MS-Office365-Filtering-Correlation-Id: 85dca25c-8428-4ca6-79a4-08dd15c5016b X-MS-Exchange-SharedMailbox-RoutingAgent-Processed: True X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|366016|1800799024|376014|7416014; X-Microsoft-Antispam-Message-Info: =?utf-8?q?kVr9Q/p+sAFyQSdvdSZ9BMcHEHVnhhn?= =?utf-8?q?rtIXMCppVx2s2ze3qEpqcZm7ptM6Il8vJKmtwSnW5od6g9FNe/Rk1i+RjA1dbNIV3?= =?utf-8?q?VKIYmpalIUYzE2ufbR/jmto8HYPbpYDBgi4F3zWAOMP8sAX/DVVVuQVRciowqSmAL?= =?utf-8?q?lC2iSPICvF76LpI73WNFV8l4bsDTNtUaD4qpHM8RrMvfASlc95NIkU0cqgHsc0+i/?= =?utf-8?q?FTMSQ7Jjh9UHNp2SSegpcXXDE4495Iz1d67EppVXz2TNJjzBn1SOGuIuFR9cthqmr?= =?utf-8?q?Ry9u4Hmzb+eeCiU2Tlv0v0CbfQtMnmHSO8O9exrj/nk1ROFT28zVNzQYAKShGXaTx?= =?utf-8?q?3UgO4yJOHBjAmlVoLtS6/CJzGYASZgW+uIoG3Q6Say/tgL+cJO8XX6sutZa3/LXqy?= =?utf-8?q?22dzUIN2DlW4h5e1kBgwFPTtyc6IehQD0gZ5CUpOio2NqlEGi9pEJoh1fEDGxakIZ?= =?utf-8?q?1LEJbWbqqZfD7R6n+LnCtUwpXWhyYqAxocWrozVRGfQDqky83RCp5o3/XwjQvuKhj?= =?utf-8?q?uyya3mPIfk7US0aTQXoizcI4DLuN95GpDU+b7LoZ9QuVozsE+13lcdHTsx9FBDdJJ?= =?utf-8?q?OEy/4jKC/6cfAENKFsA3XJz3Lx05rJPwTMHcC1e98WcnApvXBhZdiSG2W2f9vvMSZ?= =?utf-8?q?JL5mVKaHWBH+xIV7qZe0opcHL+dUT6WG8up91fmNrevbxreLoGMLM7HVL5/e5Utyv?= =?utf-8?q?zHKTLvzvSxQuW02lO4rcUR7VQuu1D2UBSsgmF3fT2j2AcG1cflHShpZ38h0ccZFjl?= =?utf-8?q?NBYxqTos9kVWT++pJRB2Ok/11Ctzl0QXCy6+933tPB5ylLmo3es5H1i/oqBG1PNmP?= =?utf-8?q?1R4dm3s2NcPE85+SbdRpZzKP3UhWbdNRhYJdxaSJG3Yf8RkWmgZajkDIEpFYhanSm?= =?utf-8?q?yeO/Z7YRPCo72eNsSYP55ABlykNsozWPbMJrvUw0tV66xXsBiUuVXNNtyDmlEPh/i?= =?utf-8?q?icjSH5zl9VJzb9ToBQ39jMRiwhuQ4mqoGKg0imgkolA+x5FHCK7d4AuFxL/vSqX+H?= =?utf-8?q?GqFHKFUx4mrjjjK7q+xXswIcpMlI72ChvAxsjX7N4qBmdOJUdxqqCYkuf2DLlL9kD?= =?utf-8?q?zzVR8rYmUC2KiHCYy4Z/hyWanNCElQKgnzHnKZDd8KWHy3A5yYnWeffiVBG7i4aeF?= =?utf-8?q?qNGF1feSK3b98cwHJwmYQx2+xeoUBoZdSX7lHdlIzViSssgJY4uGzJbWcI2widJNI?= =?utf-8?q?sbu/4Ivl4WbLCWQ4qhxuWupglkjMp0sblbDgAXWDjUUfsefMtOofFZlHq6tWJbDnv?= =?utf-8?q?+oPaF5SEIOR3cQ44kLPDb/Uwq+bL5oxWMoQ=3D=3D?= X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:DU0PR04MB9251.eurprd04.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230040)(366016)(1800799024)(376014)(7416014);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?utf-8?q?UcB7I6u3CzTqxtzPaVe+CQSFMgT+?= =?utf-8?q?A+Wb1Byw+BPUD+Lix694N+mvsWASuO5YjLMpQDkdp11e1AbilZ0BGXyVAAfEB6YL4?= =?utf-8?q?QKO0ertoE/wzj1RlCguhj5NGpEB5Uful5oXdexllYYaiHZDpJolU+6r1x1WT4VADM?= =?utf-8?q?/A8gJCIC10+gjRR81UmZhQePEaF1uVTTWD5akCAP5jekhta42vWmbFTRsnqrVChqM?= =?utf-8?q?HIP7ac/GeRe+aRALgiSYE5jY4T71jKmUPs9AvLj0ebNzvK82QBwU2mEPXAW5sLAgV?= =?utf-8?q?EyPButDoUjPioUw6a65mmkzTSHorTRg0wD9w9RP+MnXm+0jR82OObL20Efje7jZie?= =?utf-8?q?zf73yZT87L7Fe70OuFxRYoMsImjNP/SxTa8LDT/gZCRHEv1wJBn9wbCujGyQTaEYK?= =?utf-8?q?/i2hsXfUydMIMvjXfZD8rL5Dkx9oMSeAHyQf9zAZNZBgDPmYzLxv47U4ciz6xXeMe?= =?utf-8?q?TVD4RXH/OjcGb02hEmaTp38WHfUffmpr7gsXGDo5uv9Mnji5UfFGwIIiRYK11C/AM?= =?utf-8?q?NNIBEour8lXdtI82FFz1G6g9MbDxO81WoKNa/19WsUBwnICjYLdwrukJo5/WHVGjj?= =?utf-8?q?+dJ2QrNYqLLf9PxaecMBFwA87Vf6/3cgK6LxhxpH38qexOsy649CADBptgCsnLOiL?= =?utf-8?q?kfjR4Bq8livA/lfawz8Oei4ULfUy22iMfrTgJ4RUUz+Nf6blXdR4wplGdO3f/jRQA?= =?utf-8?q?GN05pepLtJhKl4NXLeSMtPiLOpAmm2cY5xQtpNZCrNwlXqIfuDA31XH1OTI9bQ4/r?= =?utf-8?q?/0BPFFAEt4LmU4rfU2dkQ0eOMjEsMCcHDiFiFQwvz8WE6WYcfEjH65+Pqzwa4hYNa?= =?utf-8?q?9xsWiG2VSqwm11Ve0izFv3OBAbf9eLLuhHysnKQXosbvlAhI5jAxX+PxnEx3Tvucj?= =?utf-8?q?RECmQLZJ/fAVrszLX4Hp40MO63VG1VbB+Kk4+nhHnXN+u+UbAMHqjPLhRy4yT7pfb?= =?utf-8?q?QV9sGJD7FK0nLQ0PWzpAU9jn5BMZSiNMDiSof/X7WlK55ZxiceXVdwpohEwPAzJad?= =?utf-8?q?1b8yiAsfHSd9c4cosF5MrMunF76LHMwc9fSZGIwHN3888V1k+0gL3VbaOpgqNoWiL?= =?utf-8?q?r83uFzwaoosCWR0Lz+Ip8JDvxIJTUWTfSrujeccn2Knzu78cefGU6kbsT8zH5HKq4?= =?utf-8?q?NCG5/uW33yuonyEC50TnKSCkOv8kEfO4SbbCwLpE140IxKfFwAOjNoDeg2VWDAVgd?= =?utf-8?q?6vDFwvEO4hIV8vboSaoxj+6be7seaSWfw73l5NYxITO9L3AzfdgiBzATiOQgu17AQ?= =?utf-8?q?Kfb+36FSh83SX/1synQiSWKr5HfnmYtwuWJHBSrB93TmGO/U9NwBZ3iDfpZsJvJaB?= =?utf-8?q?ZLfYCphquizzdZPrRUgMuCh4YzlyefND77soueYzf2EDv109XpytDPsfYIsrGcKVW?= =?utf-8?q?d7eVpl0YyEu4LEcGdzdfJusBgWXZL94Tak05BSG8jYiR6MyIEh6uJ6jJDCisC2HZp?= =?utf-8?q?qsMxSsuK7IRIhCy/9R5r0pnphXrJcEbF04saWHaiKG7iNWuQj0herDftitZ0mZREv?= =?utf-8?q?4CDlPBtHZNSaA3fKoBHlRSHKEQr/MFvdmA=3D=3D?= X-OriginatorOrg: oss.nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: 85dca25c-8428-4ca6-79a4-08dd15c5016b X-MS-Exchange-CrossTenant-AuthSource: DU0PR04MB9251.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 06 Dec 2024 07:10:03.4677 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: 2Z1z5u4Sji1e0+epgOOsV+pKUkBu5uhFcocw79bMrGjkVQtdmXwvDU4S/5hbEhCFDASUfQ48EWuCWhIdNUTwdS2WY9h+oQsuxHAZpKdzaxE= X-MS-Exchange-Transport-CrossTenantHeadersStamped: DB9PR04MB9889 From: Ciprian Marian Costea Add a RTC driver for NXP S32G2/S32G3 SoCs. RTC tracks clock time during system suspend. It can be a wakeup source for the S32G2/S32G3 SoC based boards. The RTC module from S32G2/S32G3 is not battery-powered and it is not kept alive during system reset. Co-developed-by: Bogdan Hamciuc Signed-off-by: Bogdan Hamciuc Co-developed-by: Ghennadi Procopciuc Signed-off-by: Ghennadi Procopciuc Signed-off-by: Ciprian Marian Costea --- drivers/rtc/Kconfig | 11 + drivers/rtc/Makefile | 1 + drivers/rtc/rtc-s32g.c | 529 +++++++++++++++++++++++++++++++++++++++++ 3 files changed, 541 insertions(+) create mode 100644 drivers/rtc/rtc-s32g.c diff --git a/drivers/rtc/Kconfig b/drivers/rtc/Kconfig index a60bcc791a48..25ee7c6d8748 100644 --- a/drivers/rtc/Kconfig +++ b/drivers/rtc/Kconfig @@ -2103,4 +2103,15 @@ config RTC_DRV_AMLOGIC_A4 This driver can also be built as a module. If so, the module will be called "rtc-amlogic-a4". +config RTC_DRV_S32G + tristate "RTC driver for S32G2/S32G3 SoCs" + depends on ARCH_S32 || COMPILE_TEST + depends on COMMON_CLK + help + Say yes to enable RTC driver for platforms based on the + S32G2/S32G3 SoC family. + + This RTC module can be used as a wakeup source. + Please note that it is not battery-powered. + endif # RTC_CLASS diff --git a/drivers/rtc/Makefile b/drivers/rtc/Makefile index 489b4ab07068..e4b616ecd5ce 100644 --- a/drivers/rtc/Makefile +++ b/drivers/rtc/Makefile @@ -161,6 +161,7 @@ obj-$(CONFIG_RTC_DRV_RX8111) += rtc-rx8111.o obj-$(CONFIG_RTC_DRV_RX8581) += rtc-rx8581.o obj-$(CONFIG_RTC_DRV_RZN1) += rtc-rzn1.o obj-$(CONFIG_RTC_DRV_RENESAS_RTCA3) += rtc-renesas-rtca3.o +obj-$(CONFIG_RTC_DRV_S32G) += rtc-s32g.o obj-$(CONFIG_RTC_DRV_S35390A) += rtc-s35390a.o obj-$(CONFIG_RTC_DRV_S3C) += rtc-s3c.o obj-$(CONFIG_RTC_DRV_S5M) += rtc-s5m.o diff --git a/drivers/rtc/rtc-s32g.c b/drivers/rtc/rtc-s32g.c new file mode 100644 index 000000000000..0989b6f2a613 --- /dev/null +++ b/drivers/rtc/rtc-s32g.c @@ -0,0 +1,529 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright 2024 NXP + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define RTCC_OFFSET 0x4ul +#define RTCS_OFFSET 0x8ul +#define RTCCNT_OFFSET 0xCul +#define APIVAL_OFFSET 0x10ul +#define RTCVAL_OFFSET 0x14ul + +/* RTCC fields */ +#define RTCC_CNTEN BIT(31) +#define RTCC_RTCIE BIT(30) +#define RTCC_APIEN BIT(15) +#define RTCC_APIIE BIT(14) +#define RTCC_CLKSEL_MASK GENMASK(13, 12) +#define RTCC_DIV512EN BIT(11) +#define RTCC_DIV32EN BIT(10) + +/* RTCS fields */ +#define RTCS_RTCF BIT(29) +#define RTCS_INV_RTC BIT(18) +#define RTCS_APIF BIT(13) + +#define RTCCNT_MAX_VAL GENMASK(31, 0) +#define RTC_SYNCH_TIMEOUT (100 * USEC_PER_MSEC) + +#define RTC_CLK_MUX_SIZE 4 + +/* + * S32G2 and S32G3 SoCs have RTC clock source1 reserved and + * should not be used. + */ +#define RTC_CLK_SRC1_RESERVED BIT(1) + +enum { + DIV1 = 1, + DIV32 = 32, + DIV512 = 512, + DIV512_32 = 16384 +}; + +static const char *rtc_clk_src[RTC_CLK_MUX_SIZE] = { + "source0", + "source1", + "source2", + "source3" +}; + +struct rtc_time_base { + s64 sec; + u64 cycles; + struct rtc_time tm; +}; + +struct rtc_priv { + struct rtc_device *rdev; + void __iomem *rtc_base; + struct clk *ipg; + struct clk *clk_src; + const struct rtc_soc_data *rtc_data; + struct rtc_time_base base; + u64 rtc_hz; + int irq; + int clk_src_idx; +}; + +struct rtc_soc_data { + u32 clk_div; + u32 reserved_clk_mask; +}; + +static const struct rtc_soc_data rtc_s32g2_data = { + .clk_div = DIV512, + .reserved_clk_mask = RTC_CLK_SRC1_RESERVED, +}; + +static u64 cycles_to_sec(u64 hz, u64 cycles) +{ + return div_u64(cycles, hz); +} + +/** + * sec_to_rtcval - Convert a number of seconds to a value suitable for + * RTCVAL in our clock's + * current configuration. + * @priv: Pointer to the 'rtc_priv' structure + * @seconds: Number of seconds to convert + * @rtcval: The value to go into RTCVAL[RTCVAL] + * + * Return: 0 for success, -EINVAL if @seconds push the counter past the + * 32bit register range + */ +static int sec_to_rtcval(const struct rtc_priv *priv, + unsigned long seconds, u32 *rtcval) +{ + u32 delta_cnt; + + if (!seconds || seconds > cycles_to_sec(priv->rtc_hz, RTCCNT_MAX_VAL)) + return -EINVAL; + + /* + * RTCCNT is read-only; we must return a value relative to the + * current value of the counter (and hope we don't linger around + * too much before we get to enable the interrupt) + */ + delta_cnt = seconds * priv->rtc_hz; + *rtcval = delta_cnt + ioread32(priv->rtc_base + RTCCNT_OFFSET); + + return 0; +} + +static irqreturn_t s32g_rtc_handler(int irq, void *dev) +{ + struct rtc_priv *priv = platform_get_drvdata(dev); + u32 status; + + status = ioread32(priv->rtc_base + RTCS_OFFSET); + + if (status & RTCS_RTCF) { + iowrite32(0x0, priv->rtc_base + RTCVAL_OFFSET); + iowrite32(status | RTCS_RTCF, priv->rtc_base + RTCS_OFFSET); + rtc_update_irq(priv->rdev, 1, RTC_AF); + } + + if (status & RTCS_APIF) { + iowrite32(status | RTCS_APIF, priv->rtc_base + RTCS_OFFSET); + rtc_update_irq(priv->rdev, 1, RTC_PF); + } + + return IRQ_HANDLED; +} + +static s64 s32g_rtc_get_time_or_alrm(struct rtc_priv *priv, + u32 offset) +{ + u32 counter; + + counter = ioread32(priv->rtc_base + offset); + + if (counter < priv->base.cycles) + return -EINVAL; + + counter -= priv->base.cycles; + + return priv->base.sec + cycles_to_sec(priv->rtc_hz, counter); +} + +static int s32g_rtc_read_time(struct device *dev, + struct rtc_time *tm) +{ + struct rtc_priv *priv = dev_get_drvdata(dev); + s64 sec; + + sec = s32g_rtc_get_time_or_alrm(priv, RTCCNT_OFFSET); + if (sec < 0) + return -EINVAL; + + rtc_time64_to_tm(sec, tm); + + return 0; +} + +static int s32g_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm) +{ + struct rtc_priv *priv = dev_get_drvdata(dev); + u32 rtcc, rtccnt, rtcval; + s64 sec; + + sec = s32g_rtc_get_time_or_alrm(priv, RTCVAL_OFFSET); + if (sec < 0) + return -EINVAL; + + rtc_time64_to_tm(sec, &alrm->time); + + rtcc = ioread32(priv->rtc_base + RTCC_OFFSET); + alrm->enabled = sec && (rtcc & RTCC_RTCIE); + + alrm->pending = 0; + if (alrm->enabled) { + rtccnt = ioread32(priv->rtc_base + RTCCNT_OFFSET); + rtcval = ioread32(priv->rtc_base + RTCVAL_OFFSET); + + if (rtccnt < rtcval) + alrm->pending = 1; + } + + return 0; +} + +static int s32g_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled) +{ + struct rtc_priv *priv = dev_get_drvdata(dev); + u32 rtcc; + + if (!priv->irq) + return -EIO; + + rtcc = ioread32(priv->rtc_base + RTCC_OFFSET); + if (enabled) + rtcc |= RTCC_RTCIE; + + iowrite32(rtcc, priv->rtc_base + RTCC_OFFSET); + + return 0; +} + +static int s32g_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm) +{ + struct rtc_priv *priv = dev_get_drvdata(dev); + struct rtc_time time_crt; + long long t_crt, t_alrm; + u32 rtcval, rtcs; + int ret = 0; + + iowrite32(0x0, priv->rtc_base + RTCVAL_OFFSET); + + t_alrm = rtc_tm_to_time64(&alrm->time); + + /* + * Assuming the alarm is being set relative to the same time + * returned by our s32g_rtc_read_time callback + */ + ret = s32g_rtc_read_time(dev, &time_crt); + if (ret) + return ret; + + t_crt = rtc_tm_to_time64(&time_crt); + ret = sec_to_rtcval(priv, t_alrm - t_crt, &rtcval); + if (ret) { + dev_warn(dev, "Alarm is set too far in the future\n"); + return -ERANGE; + } + + ret = read_poll_timeout(ioread32, rtcs, !(rtcs & RTCS_INV_RTC), + 0, RTC_SYNCH_TIMEOUT, false, priv->rtc_base + RTCS_OFFSET); + if (ret) + return ret; + + iowrite32(rtcval, priv->rtc_base + RTCVAL_OFFSET); + + return 0; +} + +static int s32g_rtc_set_time(struct device *dev, + struct rtc_time *time) +{ + struct rtc_priv *priv = dev_get_drvdata(dev); + + priv->base.cycles = ioread32(priv->rtc_base + RTCCNT_OFFSET); + priv->base.sec = rtc_tm_to_time64(time); + + return 0; +} + +/* + * Disable the 32-bit free running counter. + * This allows Clock Source and Divisors selection + * to be performed without causing synchronization issues. + */ +static void s32g_rtc_disable(struct rtc_priv *priv) +{ + u32 rtcc = ioread32(priv->rtc_base + RTCC_OFFSET); + + rtcc &= ~RTCC_CNTEN; + iowrite32(rtcc, priv->rtc_base + RTCC_OFFSET); +} + +static void s32g_rtc_enable(struct rtc_priv *priv) +{ + u32 rtcc = ioread32(priv->rtc_base + RTCC_OFFSET); + + rtcc |= RTCC_CNTEN; + iowrite32(rtcc, priv->rtc_base + RTCC_OFFSET); +} + +static int rtc_clk_src_setup(struct rtc_priv *priv) +{ + u32 rtcc = 0; + + if (priv->rtc_data->reserved_clk_mask & (1 << priv->clk_src_idx)) + return -EOPNOTSUPP; + + rtcc = FIELD_PREP(RTCC_CLKSEL_MASK, priv->clk_src_idx); + + switch (priv->rtc_data->clk_div) { + case DIV512_32: + rtcc |= RTCC_DIV512EN; + rtcc |= RTCC_DIV32EN; + break; + case DIV512: + rtcc |= RTCC_DIV512EN; + break; + case DIV32: + rtcc |= RTCC_DIV32EN; + break; + case DIV1: + break; + default: + return -EINVAL; + } + + rtcc |= RTCC_RTCIE; + /* + * Make sure the CNTEN is 0 before we configure + * the clock source and dividers. + */ + s32g_rtc_disable(priv); + iowrite32(rtcc, priv->rtc_base + RTCC_OFFSET); + s32g_rtc_enable(priv); + + return 0; +} + +static const struct rtc_class_ops rtc_ops = { + .read_time = s32g_rtc_read_time, + .set_time = s32g_rtc_set_time, + .read_alarm = s32g_rtc_read_alarm, + .set_alarm = s32g_rtc_set_alarm, + .alarm_irq_enable = s32g_rtc_alarm_irq_enable, +}; + +static int rtc_clk_dts_setup(struct rtc_priv *priv, + struct device *dev) +{ + int i; + + priv->ipg = devm_clk_get_enabled(dev, "ipg"); + if (IS_ERR(priv->ipg)) + return dev_err_probe(dev, PTR_ERR(priv->ipg), + "Failed to get 'ipg' clock\n"); + + for (i = 0; i < RTC_CLK_MUX_SIZE; i++) { + priv->clk_src = devm_clk_get_enabled(dev, rtc_clk_src[i]); + if (!IS_ERR(priv->clk_src)) { + priv->clk_src_idx = i; + break; + } + } + + if (IS_ERR(priv->clk_src)) + return dev_err_probe(dev, PTR_ERR(priv->clk_src), + "Failed to get rtc module clock source\n"); + + return 0; +} + +static int s32g_rtc_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct rtc_priv *priv; + int ret = 0; + + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + priv->rtc_data = of_device_get_match_data(dev); + if (!priv->rtc_data) + return -ENODEV; + + priv->rtc_base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(priv->rtc_base)) + return PTR_ERR(priv->rtc_base); + + device_init_wakeup(dev, true); + + ret = rtc_clk_dts_setup(priv, dev); + if (ret) + return ret; + + priv->rdev = devm_rtc_allocate_device(dev); + if (IS_ERR(priv->rdev)) + return PTR_ERR(priv->rdev); + + ret = rtc_clk_src_setup(priv); + if (ret) + return ret; + + priv->rtc_hz = clk_get_rate(priv->clk_src); + if (!priv->rtc_hz) { + dev_err(dev, "Failed to get RTC frequency\n"); + ret = -EINVAL; + goto disable_rtc; + } + + priv->rtc_hz /= priv->rtc_data->clk_div; + + platform_set_drvdata(pdev, priv); + priv->rdev->ops = &rtc_ops; + + priv->irq = platform_get_irq(pdev, 0); + if (priv->irq < 0) { + ret = priv->irq; + goto disable_rtc; + } + + ret = devm_request_irq(dev, priv->irq, + s32g_rtc_handler, 0, dev_name(dev), pdev); + if (ret) { + dev_err(dev, "Request interrupt %d failed, error: %d\n", + priv->irq, ret); + goto disable_rtc; + } + + ret = devm_rtc_register_device(priv->rdev); + if (ret) + goto disable_rtc; + + return 0; + +disable_rtc: + s32g_rtc_disable(priv); + return ret; +} + +static void s32g_enable_api_irq(struct device *dev, unsigned int enabled) +{ + struct rtc_priv *priv = dev_get_drvdata(dev); + u32 api_irq = RTCC_APIEN | RTCC_APIIE; + u32 rtcc; + + rtcc = ioread32(priv->rtc_base + RTCC_OFFSET); + if (enabled) + rtcc |= api_irq; + else + rtcc &= ~api_irq; + iowrite32(rtcc, priv->rtc_base + RTCC_OFFSET); +} + +static int s32g_rtc_suspend(struct device *dev) +{ + struct rtc_priv *init_priv = dev_get_drvdata(dev); + struct rtc_priv priv; + long long base_sec; + u32 rtcval, rtccnt, offset; + int ret = 0; + u32 sec; + + if (!device_may_wakeup(dev)) + return 0; + + /* Save last known timestamp */ + ret = s32g_rtc_read_time(dev, &init_priv->base.tm); + if (ret) + return ret; + + /* + * Use a local copy of the RTC control block to + * avoid restoring it on resume path. + */ + memcpy(&priv, init_priv, sizeof(priv)); + + rtccnt = ioread32(init_priv->rtc_base + RTCCNT_OFFSET); + rtcval = ioread32(init_priv->rtc_base + RTCVAL_OFFSET); + offset = rtcval - rtccnt; + sec = cycles_to_sec(init_priv->rtc_hz, offset); + + /* Adjust for the number of seconds we'll be asleep */ + base_sec = rtc_tm_to_time64(&init_priv->base.tm); + base_sec += sec; + rtc_time64_to_tm(base_sec, &init_priv->base.tm); + + ret = sec_to_rtcval(&priv, sec, &rtcval); + if (ret) { + dev_warn(dev, "Alarm is too far in the future\n"); + return -ERANGE; + } + + s32g_enable_api_irq(dev, 1); + iowrite32(offset, priv.rtc_base + APIVAL_OFFSET); + + return ret; +} + +static int s32g_rtc_resume(struct device *dev) +{ + struct rtc_priv *priv = dev_get_drvdata(dev); + int ret; + + if (!device_may_wakeup(dev)) + return 0; + + /* Disable wake-up interrupts */ + s32g_enable_api_irq(dev, 0); + + ret = rtc_clk_src_setup(priv); + if (ret) + return ret; + + /* + * Now RTCCNT has just been reset, and is out of sync with priv->base; + * reapply the saved time settings. + */ + return s32g_rtc_set_time(dev, &priv->base.tm); +} + +static const struct of_device_id rtc_dt_ids[] = { + { .compatible = "nxp,s32g2-rtc", .data = &rtc_s32g2_data}, + { /* sentinel */ }, +}; + +static DEFINE_SIMPLE_DEV_PM_OPS(s32g_rtc_pm_ops, + s32g_rtc_suspend, s32g_rtc_resume); + +static struct platform_driver s32g_rtc_driver = { + .driver = { + .name = "s32g-rtc", + .pm = pm_sleep_ptr(&s32g_rtc_pm_ops), + .of_match_table = rtc_dt_ids, + }, + .probe = s32g_rtc_probe, +}; +module_platform_driver(s32g_rtc_driver); + +MODULE_AUTHOR("NXP"); +MODULE_DESCRIPTION("NXP RTC driver for S32G2/S32G3"); +MODULE_LICENSE("GPL");