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Fri, 20 Dec 2024 12:39:25 +0000 Received: from DU0PR04MB9251.eurprd04.prod.outlook.com ([fe80::708f:69ee:15df:6ebd]) by DU0PR04MB9251.eurprd04.prod.outlook.com ([fe80::708f:69ee:15df:6ebd%5]) with mapi id 15.20.8272.013; Fri, 20 Dec 2024 12:39:24 +0000 From: Ciprian Costea To: Chester Lin , Matthias Brugger , Ghennadi Procopciuc , Shawn Guo , Sascha Hauer , Fabio Estevam , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Pengutronix Kernel Team , linux-arm-kernel@lists.infradead.org, imx@lists.linux.dev, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, NXP S32 Linux , Christophe Lizzi , Alberto Ruiz , Enric Balletbo , Ciprian Marian Costea Subject: [PATCH v4 1/4] arm64: dts: s32g: add 'I2C' common board support Date: Fri, 20 Dec 2024 14:39:13 +0200 Message-ID: <20241220123916.1452582-2-ciprianmarian.costea@oss.nxp.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241220123916.1452582-1-ciprianmarian.costea@oss.nxp.com> References: <20241220123916.1452582-1-ciprianmarian.costea@oss.nxp.com> X-ClientProxiedBy: AM0PR02CA0020.eurprd02.prod.outlook.com (2603:10a6:208:3e::33) To DU0PR04MB9251.eurprd04.prod.outlook.com (2603:10a6:10:352::15) Precedence: bulk X-Mailing-List: imx@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DU0PR04MB9251:EE_|GV1PR04MB9516:EE_ X-MS-Office365-Filtering-Correlation-Id: 06a94e1a-fd13-468a-92c9-08dd20f355fb X-MS-Exchange-SharedMailbox-RoutingAgent-Processed: True X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|366016|7416014|1800799024; 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Specific S32G2/S32G3 based board 'i2c' dts device support will be added in further commits. Signed-off-by: Ciprian Marian Costea --- arch/arm64/boot/dts/freescale/s32g2.dtsi | 55 ++++++++++++++++++++++ arch/arm64/boot/dts/freescale/s32g3.dtsi | 60 ++++++++++++++++++++++++ 2 files changed, 115 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/s32g2.dtsi b/arch/arm64/boot/dts/freescale/s32g2.dtsi index 7be430b78c83..1a9683c234b7 100644 --- a/arch/arm64/boot/dts/freescale/s32g2.dtsi +++ b/arch/arm64/boot/dts/freescale/s32g2.dtsi @@ -333,6 +333,39 @@ uart1: serial@401cc000 { status = "disabled"; }; + i2c0: i2c@401e4000 { + compatible = "nxp,s32g2-i2c"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x401e4000 0x1000>; + interrupts = ; + clocks = <&clks 40>; + clock-names = "ipg"; + status = "disabled"; + }; + + i2c1: i2c@401e8000 { + compatible = "nxp,s32g2-i2c"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x401e8000 0x1000>; + interrupts = ; + clocks = <&clks 40>; + clock-names = "ipg"; + status = "disabled"; + }; + + i2c2: i2c@401ec000 { + compatible = "nxp,s32g2-i2c"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x401ec000 0x1000>; + interrupts = ; + clocks = <&clks 40>; + clock-names = "ipg"; + status = "disabled"; + }; + uart2: serial@402bc000 { compatible = "nxp,s32g2-linflexuart", "fsl,s32v234-linflexuart"; @@ -341,6 +374,28 @@ uart2: serial@402bc000 { status = "disabled"; }; + i2c3: i2c@402d8000 { + compatible = "nxp,s32g2-i2c"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x402d8000 0x1000>; + interrupts = ; + clocks = <&clks 40>; + clock-names = "ipg"; + status = "disabled"; + }; + + i2c4: i2c@402dc000 { + compatible = "nxp,s32g2-i2c"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x402dc000 0x1000>; + interrupts = ; + clocks = <&clks 40>; + clock-names = "ipg"; + status = "disabled"; + }; + usdhc0: mmc@402f0000 { compatible = "nxp,s32g2-usdhc"; reg = <0x402f0000 0x1000>; diff --git a/arch/arm64/boot/dts/freescale/s32g3.dtsi b/arch/arm64/boot/dts/freescale/s32g3.dtsi index 6c572ffe37ca..5d28b439906d 100644 --- a/arch/arm64/boot/dts/freescale/s32g3.dtsi +++ b/arch/arm64/boot/dts/freescale/s32g3.dtsi @@ -390,6 +390,42 @@ uart1: serial@401cc000 { status = "disabled"; }; + i2c0: i2c@401e4000 { + compatible = "nxp,s32g3-i2c", + "nxp,s32g2-i2c"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x401e4000 0x1000>; + interrupts = ; + clocks = <&clks 40>; + clock-names = "ipg"; + status = "disabled"; + }; + + i2c1: i2c@401e8000 { + compatible = "nxp,s32g3-i2c", + "nxp,s32g2-i2c"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x401e8000 0x1000>; + interrupts = ; + clocks = <&clks 40>; + clock-names = "ipg"; + status = "disabled"; + }; + + i2c2: i2c@401ec000 { + compatible = "nxp,s32g3-i2c", + "nxp,s32g2-i2c"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x401ec000 0x1000>; + interrupts = ; + clocks = <&clks 40>; + clock-names = "ipg"; + status = "disabled"; + }; + uart2: serial@402bc000 { compatible = "nxp,s32g3-linflexuart", "fsl,s32v234-linflexuart"; @@ -398,6 +434,30 @@ uart2: serial@402bc000 { status = "disabled"; }; + i2c3: i2c@402d8000 { + compatible = "nxp,s32g3-i2c", + "nxp,s32g2-i2c"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x402d8000 0x1000>; + interrupts = ; + clocks = <&clks 40>; + clock-names = "ipg"; + status = "disabled"; + }; + + i2c4: i2c@402dc000 { + compatible = "nxp,s32g3-i2c", + "nxp,s32g2-i2c"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x402dc000 0x1000>; + interrupts = ; + clocks = <&clks 40>; + clock-names = "ipg"; + status = "disabled"; + }; + usdhc0: mmc@402f0000 { compatible = "nxp,s32g3-usdhc", "nxp,s32g2-usdhc";