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[79.30.28.209]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-ab384fcd73dsm332562366b.178.2025.01.18.04.41.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 18 Jan 2025 04:41:25 -0800 (PST) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: linux-amarula@amarulasolutions.com, Dario Binacchi , Abel Vesa , Fabio Estevam , Michael Turquette , Peng Fan , Pengutronix Kernel Team , Sascha Hauer , Shawn Guo , Stephen Boyd , imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org Subject: [PATCH v9 21/23] clk: imx8mp: support spread spectrum clock generation Date: Sat, 18 Jan 2025 13:40:04 +0100 Message-ID: <20250118124044.157308-22-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250118124044.157308-1-dario.binacchi@amarulasolutions.com> References: <20250118124044.157308-1-dario.binacchi@amarulasolutions.com> Precedence: bulk X-Mailing-List: imx@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Add support for spread spectrum clock generation for the audio, video, and DRAM PLLs. Signed-off-by: Dario Binacchi --- (no changes since v1) drivers/clk/imx/clk-imx8mp.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/drivers/clk/imx/clk-imx8mp.c b/drivers/clk/imx/clk-imx8mp.c index 012cd3b52e3f..560f51d9232d 100644 --- a/drivers/clk/imx/clk-imx8mp.c +++ b/drivers/clk/imx/clk-imx8mp.c @@ -393,6 +393,7 @@ static int imx8mp_clocks_probe(struct platform_device *pdev) struct device *dev = &pdev->dev; struct device_node *np = dev->of_node, *anp; void __iomem *base; + struct imx_pll14xx_ssc ssc_conf; int err; base = devm_platform_ioremap_resource(pdev, 0); @@ -432,9 +433,21 @@ static int imx8mp_clocks_probe(struct platform_device *pdev) hws[IMX8MP_SYS_PLL3_REF_SEL] = imx_anatop_get_clk_hw(anp, IMX8MP_ANATOP_SYS_PLL3_REF_SEL); hws[IMX8MP_AUDIO_PLL1] = imx_anatop_get_clk_hw(anp, IMX8MP_ANATOP_AUDIO_PLL1); + if (!imx_clk_pll14xx_ssc_parse_dt(np, "audio_pll1", &ssc_conf)) + imx_clk_pll14xx_enable_ssc(hws[IMX8MP_AUDIO_PLL1], &ssc_conf); + hws[IMX8MP_AUDIO_PLL2] = imx_anatop_get_clk_hw(anp, IMX8MP_ANATOP_AUDIO_PLL2); + if (!imx_clk_pll14xx_ssc_parse_dt(np, "audio_pll2", &ssc_conf)) + imx_clk_pll14xx_enable_ssc(hws[IMX8MP_AUDIO_PLL2], &ssc_conf); + hws[IMX8MP_VIDEO_PLL] = imx_anatop_get_clk_hw(anp, IMX8MP_ANATOP_VIDEO_PLL); + if (!imx_clk_pll14xx_ssc_parse_dt(np, "video_pll", &ssc_conf)) + imx_clk_pll14xx_enable_ssc(hws[IMX8MP_VIDEO_PLL], &ssc_conf); + hws[IMX8MP_DRAM_PLL] = imx_anatop_get_clk_hw(anp, IMX8MP_ANATOP_DRAM_PLL); + if (!imx_clk_pll14xx_ssc_parse_dt(np, "dram_pll", &ssc_conf)) + imx_clk_pll14xx_enable_ssc(hws[IMX8MP_DRAM_PLL], &ssc_conf); + hws[IMX8MP_GPU_PLL] = imx_anatop_get_clk_hw(anp, IMX8MP_ANATOP_GPU_PLL); hws[IMX8MP_VPU_PLL] = imx_anatop_get_clk_hw(anp, IMX8MP_ANATOP_VPU_PLL); hws[IMX8MP_ARM_PLL] = imx_anatop_get_clk_hw(anp, IMX8MP_ANATOP_ARM_PLL);