| Message ID | 20250210-8qxp_camera-v3-3-324f5105accc@nxp.com (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | media: imx8: add camera support | expand |
On Mon, 10 Feb 2025 15:59:22 -0500, Frank Li wrote: > Add binding documentation for i.MX8QXP and i.MX8QM ISI. The clock-names, > power-domains, and ports differ significantly from the existing > nxp,imx8-isi.yaml. Create a new file to avoid complex if-else branches. > > Add new file to MAINTAINERS. > > Signed-off-by: Frank Li <Frank.Li@nxp.com> > --- > change from v2 to v3 > - none > change from v1 to v2 > - create new file for 8qm and 8qxp accroding rob's suggestion. > --- > .../devicetree/bindings/media/fsl,imx8qm-isi.yaml | 117 +++++++++++++++++++++ > .../devicetree/bindings/media/fsl,imx8qxp-isi.yaml | 103 ++++++++++++++++++ > MAINTAINERS | 1 + > 3 files changed, 221 insertions(+) > Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Hi Frank, Thank you for the patch. On Mon, Feb 10, 2025 at 03:59:22PM -0500, Frank Li wrote: > Add binding documentation for i.MX8QXP and i.MX8QM ISI. The clock-names, > power-domains, and ports differ significantly from the existing > nxp,imx8-isi.yaml. Create a new file to avoid complex if-else branches. Mixed feelings about having different bindings files for what is essentially the same IP, but I won't object. > Add new file to MAINTAINERS. > > Signed-off-by: Frank Li <Frank.Li@nxp.com> > --- > change from v2 to v3 > - none > change from v1 to v2 > - create new file for 8qm and 8qxp accroding rob's suggestion. > --- > .../devicetree/bindings/media/fsl,imx8qm-isi.yaml | 117 +++++++++++++++++++++ > .../devicetree/bindings/media/fsl,imx8qxp-isi.yaml | 103 ++++++++++++++++++ > MAINTAINERS | 1 + > 3 files changed, 221 insertions(+) > > diff --git a/Documentation/devicetree/bindings/media/fsl,imx8qm-isi.yaml b/Documentation/devicetree/bindings/media/fsl,imx8qm-isi.yaml > new file mode 100644 > index 0000000000000..61c551673e2a4 > --- /dev/null > +++ b/Documentation/devicetree/bindings/media/fsl,imx8qm-isi.yaml > @@ -0,0 +1,117 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/media/fsl,imx8qm-isi.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: i.MX8QM Image Sensing Interface > + > +maintainers: > + - Frank Li <Frank.Li@nxp.com> > + > +description: > + The Image Sensing Interface (ISI) combines image processing pipelines with > + DMA engines to process and capture frames originating from a variety of > + sources. The inputs to the ISI go through Pixel Link interfaces, and their > + number and nature is SoC-dependent. They cover both capture interfaces (MIPI > + CSI-2 RX, HDMI RX, ...) and display engine outputs for writeback support. > + > +properties: > + compatible: > + enum: > + - fsl,imx8qm-isi > + > + reg: > + maxItems: 1 > + > + clocks: > + maxItems: 8 > + > + clock-names: > + items: > + - const: per0 > + - const: per1 > + - const: per2 > + - const: per3 > + - const: per4 > + - const: per5 > + - const: per6 > + - const: per7 > + > + interrupts: > + maxItems: 8 > + > + power-domains: > + maxItems: 8 This surprises me. The reference manual does list 8 clocks and interrupts, but only 6 channels in the ISI section (for instance in 15.6.1.1.4). Which one is wrong ? > + > + ports: > + $ref: /schemas/graph.yaml#/properties/ports > + properties: > + port@2: > + $ref: /schemas/graph.yaml#/properties/port > + description: MIPI CSI-2 RX 0 > + port@3: > + $ref: /schemas/graph.yaml#/properties/port > + description: MIPI CSI-2 RX 1 > + port@4: > + $ref: /schemas/graph.yaml#/properties/port > + description: HDMI RX Figure 15-59 in the reference manual list MIPI CSI-2 RX 0 and RX 1 as connected to inputs 0 and 1 respectively. > + > +required: > + - compatible > + - reg > + - clocks > + - clock-names > + - interrupts > + - power-domains > + - ports > + > +additionalProperties: false > + > +examples: > + - | > + #include <dt-bindings/interrupt-controller/arm-gic.h> > + #include <dt-bindings/interrupt-controller/irq.h> > + #include <dt-bindings/clock/imx8-clock.h> > + #include <dt-bindings/clock/imx8-lpcg.h> > + #include <dt-bindings/firmware/imx/rsrc.h> > + > + image-controller@58100000 { > + compatible = "fsl,imx8qm-isi"; > + reg = <0x58100000 0x90000>; The memory map in the reference manual lists the "Pixel DMA" region as ending at 0x5817ffff. Shouldn't the length of the region be 0x80000 ? > + interrupts = <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&pdma0_lpcg IMX_LPCG_CLK_0>, > + <&pdma1_lpcg IMX_LPCG_CLK_0>, > + <&pdma2_lpcg IMX_LPCG_CLK_0>, > + <&pdma3_lpcg IMX_LPCG_CLK_0>, > + <&pdma4_lpcg IMX_LPCG_CLK_0>, > + <&pdma5_lpcg IMX_LPCG_CLK_0>, > + <&pdma6_lpcg IMX_LPCG_CLK_0>, > + <&pdma7_lpcg IMX_LPCG_CLK_0>; > + clock-names = "per0", "per1", "per2", "per3", > + "per4", "per5", "per6", "per7"; > + power-domains = <&pd IMX_SC_R_ISI_CH0>, <&pd IMX_SC_R_ISI_CH1>, > + <&pd IMX_SC_R_ISI_CH2>, <&pd IMX_SC_R_ISI_CH3>, > + <&pd IMX_SC_R_ISI_CH4>, <&pd IMX_SC_R_ISI_CH5>, > + <&pd IMX_SC_R_ISI_CH6>, <&pd IMX_SC_R_ISI_CH7>; > + > + ports { > + #address-cells = <1>; > + #size-cells = <0>; > + > + port@2 { > + reg = <2>; > + endpoint { > + remote-endpoint = <&mipi_csi0_out>; > + }; > + }; > + }; > + }; > +... > diff --git a/Documentation/devicetree/bindings/media/fsl,imx8qxp-isi.yaml b/Documentation/devicetree/bindings/media/fsl,imx8qxp-isi.yaml > new file mode 100644 > index 0000000000000..818fea0e4679f > --- /dev/null > +++ b/Documentation/devicetree/bindings/media/fsl,imx8qxp-isi.yaml > @@ -0,0 +1,103 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/media/fsl,imx8qxp-isi.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: i.MX8QXP Image Sensing Interface > + > +maintainers: > + - Frank Li <Frank.Li@nxp.com> > + > +description: > + The Image Sensing Interface (ISI) combines image processing pipelines with > + DMA engines to process and capture frames originating from a variety of > + sources. The inputs to the ISI go through Pixel Link interfaces, and their > + number and nature is SoC-dependent. They cover both capture interfaces (MIPI > + CSI-2 RX, HDMI RX, ...) and display engine outputs for writeback support. > + > +properties: > + compatible: > + enum: > + - fsl,imx8qxp-isi > + > + reg: > + maxItems: 1 > + > + clocks: > + maxItems: 5 > + > + clock-names: > + items: > + - const: per0 > + - const: per4 > + - const: per5 > + - const: per6 > + - const: per7 > + > + interrupts: > + maxItems: 5 > + > + power-domains: > + maxItems: 5 Here you have 5 channels, while the reference manual lists 8 interrupts and 6 channels in the ISI documentation. > + > + ports: > + $ref: /schemas/graph.yaml#/properties/ports > + properties: > + port@2: > + $ref: /schemas/graph.yaml#/properties/port > + description: MIPI CSI-2 RX 0 > + port@6: > + $ref: /schemas/graph.yaml#/properties/port > + description: CSI-2 Parallel RX Table 15-6 in the reference manual lists the parallel port as input 4. > + > +required: > + - compatible > + - reg > + - clocks > + - clock-names > + - interrupts > + - power-domains > + - ports > + > +additionalProperties: false > + > +examples: > + - | > + #include <dt-bindings/interrupt-controller/arm-gic.h> > + #include <dt-bindings/interrupt-controller/irq.h> > + #include <dt-bindings/clock/imx8-clock.h> > + #include <dt-bindings/clock/imx8-lpcg.h> > + #include <dt-bindings/firmware/imx/rsrc.h> > + > + image-controller@58100000 { > + compatible = "fsl,imx8qxp-isi"; > + reg = <0x58100000 0x90000>; Same comment here about the registers range. > + interrupts = <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&pdma0_lpcg IMX_LPCG_CLK_0>, > + <&pdma4_lpcg IMX_LPCG_CLK_0>, > + <&pdma5_lpcg IMX_LPCG_CLK_0>, > + <&pdma6_lpcg IMX_LPCG_CLK_0>, > + <&pdma7_lpcg IMX_LPCG_CLK_0>; > + clock-names = "per0", "per4", "per5", "per6", "per7"; > + power-domains = <&pd IMX_SC_R_ISI_CH0>, <&pd IMX_SC_R_ISI_CH4>, > + <&pd IMX_SC_R_ISI_CH5>, <&pd IMX_SC_R_ISI_CH6>, > + <&pd IMX_SC_R_ISI_CH7>; > + > + ports { > + #address-cells = <1>; > + #size-cells = <0>; > + > + port@2 { > + reg = <2>; > + endpoint { > + remote-endpoint = <&mipi_csi0_out>; > + }; > + }; > + }; > + }; > +... > diff --git a/MAINTAINERS b/MAINTAINERS > index 40d1b7ec30fde..f243257ef7653 100644 > --- a/MAINTAINERS > +++ b/MAINTAINERS > @@ -17000,6 +17000,7 @@ NXP i.MX 8M ISI DRIVER > M: Laurent Pinchart <laurent.pinchart@ideasonboard.com> > L: linux-media@vger.kernel.org > S: Maintained > +F: Documentation/devicetree/bindings/media/fsl,imx8*-isi.yaml > F: Documentation/devicetree/bindings/media/nxp,imx8-isi.yaml Should nxp,imx8-isi.yaml be renamed to fsl,imx8-isi.yaml ? > F: drivers/media/platform/nxp/imx8-isi/ >
On Thu, Mar 27, 2025 at 08:44:25PM +0200, Laurent Pinchart wrote: > Hi Frank, > > Thank you for the patch. > > On Mon, Feb 10, 2025 at 03:59:22PM -0500, Frank Li wrote: > > Add binding documentation for i.MX8QXP and i.MX8QM ISI. The clock-names, > > power-domains, and ports differ significantly from the existing > > nxp,imx8-isi.yaml. Create a new file to avoid complex if-else branches. > > Mixed feelings about having different bindings files for what is > essentially the same IP, but I won't object. Rob suggest split it at v1. https://lore.kernel.org/all/20250203221659.GA130749-robh@kernel.org/ "I think this addition is borderline whether it should be its own schema doc. The if/then schemas are larger than the main part. The ports are not even the same." > > > Add new file to MAINTAINERS. > > > > Signed-off-by: Frank Li <Frank.Li@nxp.com> > > --- > > change from v2 to v3 > > - none > > change from v1 to v2 > > - create new file for 8qm and 8qxp accroding rob's suggestion. > > --- > > .../devicetree/bindings/media/fsl,imx8qm-isi.yaml | 117 +++++++++++++++++++++ > > .../devicetree/bindings/media/fsl,imx8qxp-isi.yaml | 103 ++++++++++++++++++ > > MAINTAINERS | 1 + > > 3 files changed, 221 insertions(+) > > > > diff --git a/Documentation/devicetree/bindings/media/fsl,imx8qm-isi.yaml b/Documentation/devicetree/bindings/media/fsl,imx8qm-isi.yaml > > new file mode 100644 > > index 0000000000000..61c551673e2a4 > > --- /dev/null > > +++ b/Documentation/devicetree/bindings/media/fsl,imx8qm-isi.yaml > > @@ -0,0 +1,117 @@ > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > > +%YAML 1.2 > > +--- > > +$id: http://devicetree.org/schemas/media/fsl,imx8qm-isi.yaml# > > +$schema: http://devicetree.org/meta-schemas/core.yaml# > > + > > +title: i.MX8QM Image Sensing Interface > > + > > +maintainers: > > + - Frank Li <Frank.Li@nxp.com> > > + > > +description: > > + The Image Sensing Interface (ISI) combines image processing pipelines with > > + DMA engines to process and capture frames originating from a variety of > > + sources. The inputs to the ISI go through Pixel Link interfaces, and their > > + number and nature is SoC-dependent. They cover both capture interfaces (MIPI > > + CSI-2 RX, HDMI RX, ...) and display engine outputs for writeback support. > > + > > +properties: > > + compatible: > > + enum: > > + - fsl,imx8qm-isi > > + > > + reg: > > + maxItems: 1 > > + > > + clocks: > > + maxItems: 8 > > + > > + clock-names: > > + items: > > + - const: per0 > > + - const: per1 > > + - const: per2 > > + - const: per3 > > + - const: per4 > > + - const: per5 > > + - const: per6 > > + - const: per7 > > + > > + interrupts: > > + maxItems: 8 > > + > > + power-domains: > > + maxItems: 8 > > This surprises me. The reference manual does list 8 clocks and > interrupts, but only 6 channels in the ISI section (for instance in > 15.6.1.1.4). Which one is wrong ? Support 6 input, 8 output. "The crossbar is a 6 input 8 output multiplexer where each output port can be configured to connect to any of the 6 inputs." 8 irq and clocks is for output dmac. > > > + > > + ports: > > + $ref: /schemas/graph.yaml#/properties/ports > > + properties: > > + port@2: > > + $ref: /schemas/graph.yaml#/properties/port > > + description: MIPI CSI-2 RX 0 > > + port@3: > > + $ref: /schemas/graph.yaml#/properties/port > > + description: MIPI CSI-2 RX 1 > > + port@4: > > + $ref: /schemas/graph.yaml#/properties/port > > + description: HDMI RX > > Figure 15-59 in the reference manual list MIPI CSI-2 RX 0 and RX 1 as > connected to inputs 0 and 1 respectively. Reference document should be wrong, I reference another internal document 0: display control 0 1: display control 1 2: csi2 rx0 3: csi2 rx1 4: hdmi rx > > > + > > +required: > > + - compatible > > + - reg > > + - clocks > > + - clock-names > > + - interrupts > > + - power-domains > > + - ports > > + > > +additionalProperties: false > > + > > +examples: > > + - | > > + #include <dt-bindings/interrupt-controller/arm-gic.h> > > + #include <dt-bindings/interrupt-controller/irq.h> > > + #include <dt-bindings/clock/imx8-clock.h> > > + #include <dt-bindings/clock/imx8-lpcg.h> > > + #include <dt-bindings/firmware/imx/rsrc.h> > > + > > + image-controller@58100000 { > > + compatible = "fsl,imx8qm-isi"; > > + reg = <0x58100000 0x90000>; > > The memory map in the reference manual lists the "Pixel DMA" region as > ending at 0x5817ffff. Shouldn't the length of the region be 0x80000 ? Yes, it should be 0x80000. > > > + interrupts = <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, > > + <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>, > > + <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>, > > + <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>, > > + <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>, > > + <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>, > > + <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>, > > + <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>; > > + clocks = <&pdma0_lpcg IMX_LPCG_CLK_0>, > > + <&pdma1_lpcg IMX_LPCG_CLK_0>, > > + <&pdma2_lpcg IMX_LPCG_CLK_0>, > > + <&pdma3_lpcg IMX_LPCG_CLK_0>, > > + <&pdma4_lpcg IMX_LPCG_CLK_0>, > > + <&pdma5_lpcg IMX_LPCG_CLK_0>, > > + <&pdma6_lpcg IMX_LPCG_CLK_0>, > > + <&pdma7_lpcg IMX_LPCG_CLK_0>; > > + clock-names = "per0", "per1", "per2", "per3", > > + "per4", "per5", "per6", "per7"; > > + power-domains = <&pd IMX_SC_R_ISI_CH0>, <&pd IMX_SC_R_ISI_CH1>, > > + <&pd IMX_SC_R_ISI_CH2>, <&pd IMX_SC_R_ISI_CH3>, > > + <&pd IMX_SC_R_ISI_CH4>, <&pd IMX_SC_R_ISI_CH5>, > > + <&pd IMX_SC_R_ISI_CH6>, <&pd IMX_SC_R_ISI_CH7>; > > + > > + ports { > > + #address-cells = <1>; > > + #size-cells = <0>; > > + > > + port@2 { > > + reg = <2>; > > + endpoint { > > + remote-endpoint = <&mipi_csi0_out>; > > + }; > > + }; > > + }; > > + }; > > +... > > diff --git a/Documentation/devicetree/bindings/media/fsl,imx8qxp-isi.yaml b/Documentation/devicetree/bindings/media/fsl,imx8qxp-isi.yaml > > new file mode 100644 > > index 0000000000000..818fea0e4679f > > --- /dev/null > > +++ b/Documentation/devicetree/bindings/media/fsl,imx8qxp-isi.yaml > > @@ -0,0 +1,103 @@ > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > > +%YAML 1.2 > > +--- > > +$id: http://devicetree.org/schemas/media/fsl,imx8qxp-isi.yaml# > > +$schema: http://devicetree.org/meta-schemas/core.yaml# > > + > > +title: i.MX8QXP Image Sensing Interface > > + > > +maintainers: > > + - Frank Li <Frank.Li@nxp.com> > > + > > +description: > > + The Image Sensing Interface (ISI) combines image processing pipelines with > > + DMA engines to process and capture frames originating from a variety of > > + sources. The inputs to the ISI go through Pixel Link interfaces, and their > > + number and nature is SoC-dependent. They cover both capture interfaces (MIPI > > + CSI-2 RX, HDMI RX, ...) and display engine outputs for writeback support. > > + > > +properties: > > + compatible: > > + enum: > > + - fsl,imx8qxp-isi > > + > > + reg: > > + maxItems: 1 > > + > > + clocks: > > + maxItems: 5 > > + > > + clock-names: > > + items: > > + - const: per0 > > + - const: per4 > > + - const: per5 > > + - const: per6 > > + - const: per7 > > + > > + interrupts: > > + maxItems: 5 > > + > > + power-domains: > > + maxItems: 5 > > Here you have 5 channels, while the reference manual lists 8 interrupts > and 6 channels in the ISI documentation. QXP should only have 5 irqs and clocks. QM have 8, see above reply. > > > + > > + ports: > > + $ref: /schemas/graph.yaml#/properties/ports > > + properties: > > + port@2: > > + $ref: /schemas/graph.yaml#/properties/port > > + description: MIPI CSI-2 RX 0 > > + port@6: > > + $ref: /schemas/graph.yaml#/properties/port > > + description: CSI-2 Parallel RX > > Table 15-6 in the reference manual lists the parallel port as input 4. Reference manual is wrong. > > > + > > +required: > > + - compatible > > + - reg > > + - clocks > > + - clock-names > > + - interrupts > > + - power-domains > > + - ports > > + > > +additionalProperties: false > > + > > +examples: > > + - | > > + #include <dt-bindings/interrupt-controller/arm-gic.h> > > + #include <dt-bindings/interrupt-controller/irq.h> > > + #include <dt-bindings/clock/imx8-clock.h> > > + #include <dt-bindings/clock/imx8-lpcg.h> > > + #include <dt-bindings/firmware/imx/rsrc.h> > > + > > + image-controller@58100000 { > > + compatible = "fsl,imx8qxp-isi"; > > + reg = <0x58100000 0x90000>; > > Same comment here about the registers range. > > > + interrupts = <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, > > + <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>, > > + <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>, > > + <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>, > > + <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>; > > + clocks = <&pdma0_lpcg IMX_LPCG_CLK_0>, > > + <&pdma4_lpcg IMX_LPCG_CLK_0>, > > + <&pdma5_lpcg IMX_LPCG_CLK_0>, > > + <&pdma6_lpcg IMX_LPCG_CLK_0>, > > + <&pdma7_lpcg IMX_LPCG_CLK_0>; > > + clock-names = "per0", "per4", "per5", "per6", "per7"; > > + power-domains = <&pd IMX_SC_R_ISI_CH0>, <&pd IMX_SC_R_ISI_CH4>, > > + <&pd IMX_SC_R_ISI_CH5>, <&pd IMX_SC_R_ISI_CH6>, > > + <&pd IMX_SC_R_ISI_CH7>; > > + > > + ports { > > + #address-cells = <1>; > > + #size-cells = <0>; > > + > > + port@2 { > > + reg = <2>; > > + endpoint { > > + remote-endpoint = <&mipi_csi0_out>; > > + }; > > + }; > > + }; > > + }; > > +... > > diff --git a/MAINTAINERS b/MAINTAINERS > > index 40d1b7ec30fde..f243257ef7653 100644 > > --- a/MAINTAINERS > > +++ b/MAINTAINERS > > @@ -17000,6 +17000,7 @@ NXP i.MX 8M ISI DRIVER > > M: Laurent Pinchart <laurent.pinchart@ideasonboard.com> > > L: linux-media@vger.kernel.org > > S: Maintained > > +F: Documentation/devicetree/bindings/media/fsl,imx8*-isi.yaml > > F: Documentation/devicetree/bindings/media/nxp,imx8-isi.yaml > > Should nxp,imx8-isi.yaml be renamed to fsl,imx8-isi.yaml ? Suppose yes, it should match one of compatible string name. This patch have not touch nxp,imx8-isi.yaml. we may rename it later Frank > > > F: drivers/media/platform/nxp/imx8-isi/ > > > > -- > Regards, > > Laurent Pinchart
diff --git a/Documentation/devicetree/bindings/media/fsl,imx8qm-isi.yaml b/Documentation/devicetree/bindings/media/fsl,imx8qm-isi.yaml new file mode 100644 index 0000000000000..61c551673e2a4 --- /dev/null +++ b/Documentation/devicetree/bindings/media/fsl,imx8qm-isi.yaml @@ -0,0 +1,117 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/fsl,imx8qm-isi.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: i.MX8QM Image Sensing Interface + +maintainers: + - Frank Li <Frank.Li@nxp.com> + +description: + The Image Sensing Interface (ISI) combines image processing pipelines with + DMA engines to process and capture frames originating from a variety of + sources. The inputs to the ISI go through Pixel Link interfaces, and their + number and nature is SoC-dependent. They cover both capture interfaces (MIPI + CSI-2 RX, HDMI RX, ...) and display engine outputs for writeback support. + +properties: + compatible: + enum: + - fsl,imx8qm-isi + + reg: + maxItems: 1 + + clocks: + maxItems: 8 + + clock-names: + items: + - const: per0 + - const: per1 + - const: per2 + - const: per3 + - const: per4 + - const: per5 + - const: per6 + - const: per7 + + interrupts: + maxItems: 8 + + power-domains: + maxItems: 8 + + ports: + $ref: /schemas/graph.yaml#/properties/ports + properties: + port@2: + $ref: /schemas/graph.yaml#/properties/port + description: MIPI CSI-2 RX 0 + port@3: + $ref: /schemas/graph.yaml#/properties/port + description: MIPI CSI-2 RX 1 + port@4: + $ref: /schemas/graph.yaml#/properties/port + description: HDMI RX + +required: + - compatible + - reg + - clocks + - clock-names + - interrupts + - power-domains + - ports + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/interrupt-controller/irq.h> + #include <dt-bindings/clock/imx8-clock.h> + #include <dt-bindings/clock/imx8-lpcg.h> + #include <dt-bindings/firmware/imx/rsrc.h> + + image-controller@58100000 { + compatible = "fsl,imx8qm-isi"; + reg = <0x58100000 0x90000>; + interrupts = <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&pdma0_lpcg IMX_LPCG_CLK_0>, + <&pdma1_lpcg IMX_LPCG_CLK_0>, + <&pdma2_lpcg IMX_LPCG_CLK_0>, + <&pdma3_lpcg IMX_LPCG_CLK_0>, + <&pdma4_lpcg IMX_LPCG_CLK_0>, + <&pdma5_lpcg IMX_LPCG_CLK_0>, + <&pdma6_lpcg IMX_LPCG_CLK_0>, + <&pdma7_lpcg IMX_LPCG_CLK_0>; + clock-names = "per0", "per1", "per2", "per3", + "per4", "per5", "per6", "per7"; + power-domains = <&pd IMX_SC_R_ISI_CH0>, <&pd IMX_SC_R_ISI_CH1>, + <&pd IMX_SC_R_ISI_CH2>, <&pd IMX_SC_R_ISI_CH3>, + <&pd IMX_SC_R_ISI_CH4>, <&pd IMX_SC_R_ISI_CH5>, + <&pd IMX_SC_R_ISI_CH6>, <&pd IMX_SC_R_ISI_CH7>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@2 { + reg = <2>; + endpoint { + remote-endpoint = <&mipi_csi0_out>; + }; + }; + }; + }; +... diff --git a/Documentation/devicetree/bindings/media/fsl,imx8qxp-isi.yaml b/Documentation/devicetree/bindings/media/fsl,imx8qxp-isi.yaml new file mode 100644 index 0000000000000..818fea0e4679f --- /dev/null +++ b/Documentation/devicetree/bindings/media/fsl,imx8qxp-isi.yaml @@ -0,0 +1,103 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/fsl,imx8qxp-isi.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: i.MX8QXP Image Sensing Interface + +maintainers: + - Frank Li <Frank.Li@nxp.com> + +description: + The Image Sensing Interface (ISI) combines image processing pipelines with + DMA engines to process and capture frames originating from a variety of + sources. The inputs to the ISI go through Pixel Link interfaces, and their + number and nature is SoC-dependent. They cover both capture interfaces (MIPI + CSI-2 RX, HDMI RX, ...) and display engine outputs for writeback support. + +properties: + compatible: + enum: + - fsl,imx8qxp-isi + + reg: + maxItems: 1 + + clocks: + maxItems: 5 + + clock-names: + items: + - const: per0 + - const: per4 + - const: per5 + - const: per6 + - const: per7 + + interrupts: + maxItems: 5 + + power-domains: + maxItems: 5 + + ports: + $ref: /schemas/graph.yaml#/properties/ports + properties: + port@2: + $ref: /schemas/graph.yaml#/properties/port + description: MIPI CSI-2 RX 0 + port@6: + $ref: /schemas/graph.yaml#/properties/port + description: CSI-2 Parallel RX + +required: + - compatible + - reg + - clocks + - clock-names + - interrupts + - power-domains + - ports + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/interrupt-controller/irq.h> + #include <dt-bindings/clock/imx8-clock.h> + #include <dt-bindings/clock/imx8-lpcg.h> + #include <dt-bindings/firmware/imx/rsrc.h> + + image-controller@58100000 { + compatible = "fsl,imx8qxp-isi"; + reg = <0x58100000 0x90000>; + interrupts = <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&pdma0_lpcg IMX_LPCG_CLK_0>, + <&pdma4_lpcg IMX_LPCG_CLK_0>, + <&pdma5_lpcg IMX_LPCG_CLK_0>, + <&pdma6_lpcg IMX_LPCG_CLK_0>, + <&pdma7_lpcg IMX_LPCG_CLK_0>; + clock-names = "per0", "per4", "per5", "per6", "per7"; + power-domains = <&pd IMX_SC_R_ISI_CH0>, <&pd IMX_SC_R_ISI_CH4>, + <&pd IMX_SC_R_ISI_CH5>, <&pd IMX_SC_R_ISI_CH6>, + <&pd IMX_SC_R_ISI_CH7>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@2 { + reg = <2>; + endpoint { + remote-endpoint = <&mipi_csi0_out>; + }; + }; + }; + }; +... diff --git a/MAINTAINERS b/MAINTAINERS index 40d1b7ec30fde..f243257ef7653 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -17000,6 +17000,7 @@ NXP i.MX 8M ISI DRIVER M: Laurent Pinchart <laurent.pinchart@ideasonboard.com> L: linux-media@vger.kernel.org S: Maintained +F: Documentation/devicetree/bindings/media/fsl,imx8*-isi.yaml F: Documentation/devicetree/bindings/media/nxp,imx8-isi.yaml F: drivers/media/platform/nxp/imx8-isi/
Add binding documentation for i.MX8QXP and i.MX8QM ISI. The clock-names, power-domains, and ports differ significantly from the existing nxp,imx8-isi.yaml. Create a new file to avoid complex if-else branches. Add new file to MAINTAINERS. Signed-off-by: Frank Li <Frank.Li@nxp.com> --- change from v2 to v3 - none change from v1 to v2 - create new file for 8qm and 8qxp accroding rob's suggestion. --- .../devicetree/bindings/media/fsl,imx8qm-isi.yaml | 117 +++++++++++++++++++++ .../devicetree/bindings/media/fsl,imx8qxp-isi.yaml | 103 ++++++++++++++++++ MAINTAINERS | 1 + 3 files changed, 221 insertions(+)