From patchwork Tue Jul 31 02:12:40 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Navare, Manasi" X-Patchwork-Id: 10549749 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id C0C9D15E2 for ; Tue, 31 Jul 2018 02:10:42 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 9EFB62ABA9 for ; Tue, 31 Jul 2018 02:10:42 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 8F9EC2ABAC; Tue, 31 Jul 2018 02:10:42 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 30B082ABA9 for ; Tue, 31 Jul 2018 02:10:42 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 1849E898F1; Tue, 31 Jul 2018 02:10:38 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by gabe.freedesktop.org (Postfix) with ESMTPS id 29705898E1; Tue, 31 Jul 2018 02:10:37 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga006.jf.intel.com ([10.7.209.51]) by fmsmga103.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 30 Jul 2018 19:10:36 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.51,425,1526367600"; d="scan'208";a="62036695" Received: from labuser-z97x-ud5h.jf.intel.com ([10.54.75.151]) by orsmga006.jf.intel.com with ESMTP; 30 Jul 2018 19:10:36 -0700 From: Manasi Navare To: intel-gfx@lists.freedesktop.org Date: Mon, 30 Jul 2018 19:12:40 -0700 Message-Id: <1533003183-22793-1-git-send-email-manasi.d.navare@intel.com> X-Mailer: git-send-email 2.7.4 MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 00/23] Enable Display Stream Compression on eDP/DP X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: dri-devel@lists.freedesktop.org Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP Cc: dri-devel@lists.freedesktop.org VESA has developed an industry standard Display Stream Compression(DSC) for interoperable, visually lossless compression over display links to address the needs for higher resolution displays. This patch series enables DSC on Gen 10 eDP and Gen 11 eDP/DP panels. This implementation is based on VESA DP 1.4 and DSC specifications. These patches have been validated on 1080p eDP 1.4 panel with DSC support and FPGA based DP 1.4 sink device. Gaurav K Singh (6): drm/dsc: Define VESA Display Stream Compression Capabilities drm/dsc: Define the DSC 1.1 and 1.2 Line Buffer depth constants drm/i915/dsc: Define & Compute VESA DSC params drm/i915/dsc: Compute Rate Control parameters for DSC drm/i915/dp: Enable/Disable DSC in DP Sink drm/i915/dp: Disable DSC in source by disabling DSS CTL bits Manasi Navare (15): drm/dp: Add DP DSC DPCD receiver capability size define and missing SHIFT drm/i915/dp: Cache the DP/eDP DSC DPCD register set on Hotplug/eDP Init drm/dp: DRM DP helper/macros to get DP sink DSC parameters drm/i915/dp: Add helpers for Compressed BPP and Slice Count for DSC drm/i915/dp: Validate modes using max Output BPP and slice count when DSC supported drm/dp: Define payload size for DP SDP PPS packet drm/dsc: Define Display Stream Compression PPS infoframe drm/dsc: Add helpers for DSC picture parameter set infoframes drm/i915/dp: Add DSC params and DSC config to intel_crtc_state drm/i915/dp: Compute DSC pipe config in atomic check drm/i915/dp: Do not enable PSR2 if DSC is enabled drm/i915/dp: Configure i915 Picture parameter Set registers during DSC enabling drm/i915/dp: Use the existing write_infoframe() for DSC PPS SDPs drm/i915/dp: Populate DSC PPS SDP and send PPS infoframes drm/i915/dp: Configure Display stream splitter registers during DSC enable Srivatsa, Anusha (2): drm/dsc: Define Rate Control values that do not change over configurations drm/i915/icl: Add Display Stream Splitter control registers Documentation/gpu/drm-kms-helpers.rst | 12 + drivers/gpu/drm/Makefile | 2 +- drivers/gpu/drm/drm_dp_helper.c | 89 +++ drivers/gpu/drm/drm_dsc.c | 221 +++++++ drivers/gpu/drm/i915/Makefile | 3 +- drivers/gpu/drm/i915/i915_drv.h | 3 + drivers/gpu/drm/i915/i915_reg.h | 34 ++ drivers/gpu/drm/i915/intel_ddi.c | 5 + drivers/gpu/drm/i915/intel_display.c | 34 +- drivers/gpu/drm/i915/intel_display.h | 3 +- drivers/gpu/drm/i915/intel_dp.c | 325 +++++++++- drivers/gpu/drm/i915/intel_dp_mst.c | 2 +- drivers/gpu/drm/i915/intel_drv.h | 21 + drivers/gpu/drm/i915/intel_hdmi.c | 23 +- drivers/gpu/drm/i915/intel_psr.c | 10 + drivers/gpu/drm/i915/intel_vdsc.c | 1080 +++++++++++++++++++++++++++++++++ include/drm/drm_dp_helper.h | 40 ++ include/drm/drm_dsc.h | 506 +++++++++++++++ 18 files changed, 2380 insertions(+), 33 deletions(-) create mode 100644 drivers/gpu/drm/drm_dsc.c create mode 100644 drivers/gpu/drm/i915/intel_vdsc.c create mode 100644 include/drm/drm_dsc.h