| Message ID | 20190131211046.18603-1-gwan-gyeong.mun@intel.com (mailing list archive) |
|---|---|
| Headers | show |
| Series | drm/i915/dp: Preliminary support for DP YCbCr4:2:0 outputs | expand |
FWIW these are all valid checkpatch complaints. BR, Jani. On Thu, 31 Jan 2019, Patchwork <patchwork@emeril.freedesktop.org> wrote: > == Series Details == > > Series: drm/i915/dp: Preliminary support for DP YCbCr4:2:0 outputs > URL : https://patchwork.freedesktop.org/series/56059/ > State : warning > > == Summary == > > $ dim checkpatch origin/drm-tip > 646f25f459f0 drm/i915/dp: Support DP ports YUV 4:2:0 output to GEN11 > -:20: WARNING:TABSTOP: Statements should start on a tabstop > #20: FILE: drivers/gpu/drm/i915/intel_dp.c:6926: > + if (INTEL_GEN(dev_priv) >= 11) > > total: 0 errors, 1 warnings, 0 checks, 9 lines checked > 485e788bfeee drm/i915/dp: Add a config function for YCBCR420 outputs > bfebbc7e2acb drm: Add a VSC structure for handling Pixel Encoding/Colorimetry Formats > 2b312268f5ba drm/i915/dp: Program VSC Header and DB for Pixel Encoding/Colorimetry Format > -:44: ERROR:TRAILING_STATEMENTS: trailing statements should be on next line > #44: FILE: drivers/gpu/drm/i915/intel_dp.c:4412: > + if (!intel_dp->attached_connector->base.ycbcr_420_allowed) return; > > total: 1 errors, 0 warnings, 0 checks, 93 lines checked > 317c3a0c98c6 drm/i915/dp: Add a support of YCBCR 4:2:0 to DP MSA > -:41: WARNING:BLOCK_COMMENT_STYLE: Block comments should align the * on each line > #41: FILE: drivers/gpu/drm/i915/intel_ddi.c:1740: > + * indicate VSC SDP for the Pixel Encoding/Colorimetry Format. > + */ > > total: 0 errors, 1 warnings, 0 checks, 21 lines checked > 49b8aff26fa2 drm/i915/dp: Update pipe_bpp for DP YCbCr4:2:0 outputs > -:54: CHECK:SPACING: spaces preferred around that '*' (ctx:VxV) > #54: FILE: drivers/gpu/drm/i915/intel_dp.c:1770: > + bpp = min(bpp, 3*bpc/bpp_divider); > ^ > > -:54: CHECK:SPACING: spaces preferred around that '/' (ctx:VxV) > #54: FILE: drivers/gpu/drm/i915/intel_dp.c:1770: > + bpp = min(bpp, 3*bpc/bpp_divider); > ^ > > total: 0 errors, 0 warnings, 2 checks, 119 lines checked > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
On Mon, 2019-02-18 at 11:44 +0200, Jani Nikula wrote: > FWIW these are all valid checkpatch complaints. > > BR, > Jani. > > On Thu, 31 Jan 2019, Patchwork <patchwork@emeril.freedesktop.org> > wrote: > > == Series Details == > > > > Series: drm/i915/dp: Preliminary support for DP YCbCr4:2:0 outputs > > URL : https://patchwork.freedesktop.org/series/56059/ > > State : warning > > > > == Summary == > > > > $ dim checkpatch origin/drm-tip > > 646f25f459f0 drm/i915/dp: Support DP ports YUV 4:2:0 output to > > GEN11 > > -:20: WARNING:TABSTOP: Statements should start on a tabstop > > #20: FILE: drivers/gpu/drm/i915/intel_dp.c:6926: > > + if (INTEL_GEN(dev_priv) >= 11) > > > > total: 0 errors, 1 warnings, 0 checks, 9 lines checked > > 485e788bfeee drm/i915/dp: Add a config function for YCBCR420 > > outputs > > bfebbc7e2acb drm: Add a VSC structure for handling Pixel > > Encoding/Colorimetry Formats > > 2b312268f5ba drm/i915/dp: Program VSC Header and DB for Pixel > > Encoding/Colorimetry Format > > -:44: ERROR:TRAILING_STATEMENTS: trailing statements should be on > > next line > > #44: FILE: drivers/gpu/drm/i915/intel_dp.c:4412: > > + if (!intel_dp->attached_connector- > > >base.ycbcr_420_allowed) return; > > > > total: 1 errors, 0 warnings, 0 checks, 93 lines checked > > 317c3a0c98c6 drm/i915/dp: Add a support of YCBCR 4:2:0 to DP MSA > > -:41: WARNING:BLOCK_COMMENT_STYLE: Block comments should align the > > * on each line > > #41: FILE: drivers/gpu/drm/i915/intel_ddi.c:1740: > > + * indicate VSC SDP for the Pixel Encoding/Colorimetry Format. > > + */ > > > > total: 0 errors, 1 warnings, 0 checks, 21 lines checked > > 49b8aff26fa2 drm/i915/dp: Update pipe_bpp for DP YCbCr4:2:0 outputs > > -:54: CHECK:SPACING: spaces preferred around that '*' (ctx:VxV) > > #54: FILE: drivers/gpu/drm/i915/intel_dp.c:1770: > > + bpp = min(bpp, 3*bpc/bpp_divider); > > ^ > > > > -:54: CHECK:SPACING: spaces preferred around that '/' (ctx:VxV) > > #54: FILE: drivers/gpu/drm/i915/intel_dp.c:1770: > > + bpp = min(bpp, 3*bpc/bpp_divider); > > ^ > > > > total: 0 errors, 0 warnings, 2 checks, 119 lines checked > > Thank you for guiding me. I will fix all of warnings from Fi.CI.CHECKPATCH. Br, Gwan-gyeong. > > _______________________________________________ > > Intel-gfx mailing list > > Intel-gfx@lists.freedesktop.org > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
On Gen 11 platform, to enable resolutions like 5K@120 (or higher) we need to use DSC (DP 1.4) or YCbCr4:2:0 (DP 1.3 or 1.4) on DP. In order to support YCbCr4:2:0 on DP we need to program YCBCR 4:2:0 to MSA and VSC SDP. This patches are RFC patches that add a VSC structure for handling Pixel Encoding/Colorimetry Formats and program YCBCR 4:2:0 to MSA and VSC SDP. This is currently not tested, but I wanted to get some inputs on this approach. The idea of a scaling (RGB -> YCbCr4:4:4 -> YCbCr 4:2:0) is to follow the same approach used in YCbCr 4:2:0 on HDMI. Gwan-gyeong Mun (6): drm/i915/dp: Support DP ports YUV 4:2:0 output to GEN11 drm/i915/dp: Add a config function for YCBCR420 outputs drm: Add a VSC structure for handling Pixel Encoding/Colorimetry Formats drm/i915/dp: Program VSC Header and DB for Pixel Encoding/Colorimetry Format drm/i915/dp: Add a support of YCBCR 4:2:0 to DP MSA drm/i915/dp: Update pipe_bpp for DP YCbCr4:2:0 outputs drivers/gpu/drm/i915/i915_reg.h | 1 + drivers/gpu/drm/i915/intel_ddi.c | 16 +++- drivers/gpu/drm/i915/intel_dp.c | 147 +++++++++++++++++++++++++++++-- drivers/gpu/drm/i915/intel_drv.h | 2 + include/drm/drm_dp_helper.h | 17 ++++ 5 files changed, 176 insertions(+), 7 deletions(-)