| Message ID | 20190205160848.24662-1-ville.syrjala@linux.intel.com (mailing list archive) |
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| Headers | show
Return-Path: <intel-gfx-bounces@lists.freedesktop.org> Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 9CD67922 for <patchwork-intel-gfx@patchwork.kernel.org>; Tue, 5 Feb 2019 16:08:55 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 865C02A872 for <patchwork-intel-gfx@patchwork.kernel.org>; Tue, 5 Feb 2019 16:08:55 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 7268E2A7AA; Tue, 5 Feb 2019 16:08:55 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 24B8C2A7AA for <patchwork-intel-gfx@patchwork.kernel.org>; Tue, 5 Feb 2019 16:08:55 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id B9B31897F3; Tue, 5 Feb 2019 16:08:53 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) by gabe.freedesktop.org (Postfix) with ESMTPS id 7C02C89232 for <intel-gfx@lists.freedesktop.org>; Tue, 5 Feb 2019 16:08:52 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga001.jf.intel.com ([10.7.209.18]) by fmsmga104.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 05 Feb 2019 08:08:51 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.56,564,1539673200"; d="scan'208";a="136084734" Received: from stinkbox.fi.intel.com (HELO stinkbox) ([10.237.72.174]) by orsmga001.jf.intel.com with SMTP; 05 Feb 2019 08:08:49 -0800 Received: by stinkbox (sSMTP sendmail emulation); Tue, 05 Feb 2019 18:08:48 +0200 From: Ville Syrjala <ville.syrjala@linux.intel.com> To: intel-gfx@lists.freedesktop.org Date: Tue, 5 Feb 2019 18:08:35 +0200 Message-Id: <20190205160848.24662-1-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 2.19.2 MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH v2 00/13] Enable/disable gamma/csc dynamically and fix C8 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development <intel-gfx.lists.freedesktop.org> List-Unsubscribe: <https://lists.freedesktop.org/mailman/options/intel-gfx>, <mailto:intel-gfx-request@lists.freedesktop.org?subject=unsubscribe> List-Archive: <https://lists.freedesktop.org/archives/intel-gfx> List-Post: <mailto:intel-gfx@lists.freedesktop.org> List-Help: <mailto:intel-gfx-request@lists.freedesktop.org?subject=help> List-Subscribe: <https://lists.freedesktop.org/mailman/listinfo/intel-gfx>, <mailto:intel-gfx-request@lists.freedesktop.org?subject=subscribe> Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" <intel-gfx-bounces@lists.freedesktop.org> X-Virus-Scanned: ClamAV using ClamSMTP |
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Enable/disable gamma/csc dynamically and fix C8
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From: Ville Syrjälä <ville.syrjala@linux.intel.com> Rebase of the gamma/csc series. The last patch is new to fix Matt's observation that we need something to configure the DSPCNTR gamma/csc bits correctly during modeset. Ville Syrjälä (13): drm/i915: Split the gamma/csc enable bits from the plane_ctl() function drm/i915: Precompute gamma_mode drm/i915: Constify the state arguments to the color management stuff drm/i915: Pull GAMMA_MODE write out from haswell_load_luts() drm/i915: Split color mgmt based on single vs. double buffered registers drm/i915: Move LUT programming to happen after vblank waits drm/i915: Populate gamma_mode for all platforms drm/i915: Track pipe gamma enable/disable in crtc state drm/i915: Track pipe csc enable in crtc state drm/i915: Turn off pipe gamma when it's not needed drm/i915: Turn off pipe CSC when it's not needed drm/i915: Disable pipe gamma when C8 pixel format is used drm/i915: Update DSPCNTR gamma/csc bits during crtc_enable() drivers/gpu/drm/i915/i915_drv.h | 16 +- drivers/gpu/drm/i915/i915_reg.h | 14 +- drivers/gpu/drm/i915/intel_atomic_plane.c | 5 + drivers/gpu/drm/i915/intel_color.c | 381 ++++++++++++++-------- drivers/gpu/drm/i915/intel_display.c | 283 ++++++++++++---- drivers/gpu/drm/i915/intel_drv.h | 14 +- drivers/gpu/drm/i915/intel_sprite.c | 67 +++- 7 files changed, 568 insertions(+), 212 deletions(-)