mbox series

[v2,0/2] drm/i915: CTS fixes

Message ID 20190620092730.4700-1-lionel.g.landwerlin@intel.com (mailing list archive)
Headers show
Series drm/i915: CTS fixes | expand

Message

Lionel Landwerlin June 20, 2019, 9:27 a.m. UTC 
Rebased on drm-tip.

Cheers,

Lionel Landwerlin (2):
  drm/i915: whitelist PS_(DEPTH|INVOCATION)_COUNT
  drm/i915/icl: whitelist PS_(DEPTH|INVOCATION)_COUNT

 drivers/gpu/drm/i915/gt/intel_workarounds.c | 16 +++++++++++++++-
 1 file changed, 15 insertions(+), 1 deletion(-)

--
2.21.0.392.gf8f6787159e

Comments

Chris Wilson June 20, 2019, 1:41 p.m. UTC | #1 
Quoting Patchwork (2019-06-20 14:35:27)
> == Series Details ==
> 
> Series: drm/i915: CTS fixes (rev2)
> URL   : https://patchwork.freedesktop.org/series/62437/
> State : failure
> 
> == Summary ==
> 
> CI Bug Log - changes from CI_DRM_6312 -> Patchwork_13362
> ====================================================
> 
> Summary
> -------
> 
>   **FAILURE**

They all complain about:

<3> [403.297791] rcs0: Unable to write to whitelisted register 2348
[PS_INVOCATION_COUNT]

Is the complaint valid?
-Chris
Lionel Landwerlin June 20, 2019, 1:46 p.m. UTC | #2 
On 20/06/2019 16:41, Chris Wilson wrote:
> Quoting Patchwork (2019-06-20 14:35:27)
>> == Series Details ==
>>
>> Series: drm/i915: CTS fixes (rev2)
>> URL   : https://patchwork.freedesktop.org/series/62437/
>> State : failure
>>
>> == Summary ==
>>
>> CI Bug Log - changes from CI_DRM_6312 -> Patchwork_13362
>> ====================================================
>>
>> Summary
>> -------
>>
>>    **FAILURE**
> They all complain about:
>
> <3> [403.297791] rcs0: Unable to write to whitelisted register 2348
> [PS_INVOCATION_COUNT]
>
> Is the complaint valid?
> -Chris
>
Documentation says the register should be R/W...

I don't think we ever write it in Mesa so I can't really tell.


-Lionel
Chris Wilson June 21, 2019, 10:48 p.m. UTC | #3 
Quoting Lionel Landwerlin (2019-06-20 14:46:45)
> On 20/06/2019 16:41, Chris Wilson wrote:
> > Quoting Patchwork (2019-06-20 14:35:27)
> >> == Series Details ==
> >>
> >> Series: drm/i915: CTS fixes (rev2)
> >> URL   : https://patchwork.freedesktop.org/series/62437/
> >> State : failure
> >>
> >> == Summary ==
> >>
> >> CI Bug Log - changes from CI_DRM_6312 -> Patchwork_13362
> >> ====================================================
> >>
> >> Summary
> >> -------
> >>
> >>    **FAILURE**
> > They all complain about:
> >
> > <3> [403.297791] rcs0: Unable to write to whitelisted register 2348
> > [PS_INVOCATION_COUNT]
> >
> > Is the complaint valid?
> > -Chris
> >
> Documentation says the register should be R/W...

Updated the test to do a pass with privileged writes, nada.

https://intel-gfx-ci.01.org/tree/drm-tip/Trybot_4468/fi-cfl-guc/igt@i915_selftest@live_workarounds.html
<3> [249.959633] rcs0: Unable to write to whitelisted register 2348 as root
<6> [249.959656] rcs0: Whitelisted register: 2348, original value 00000000, rsvd 00000000
<6> [249.959657] Wrote 00000000, read 00000000, expect 00000000
<6> [249.959658] Wrote 01010101, read 00000000, expect 00000000
<6> [249.959659] Wrote 10100101, read 00000000, expect 00000000
<6> [249.959660] Wrote 03030303, read 00000000, expect 00000000
<6> [249.959661] Wrote 30300303, read 00000000, expect 00000000
<6> [249.959662] Wrote 05050505, read 00000000, expect 00000000
<6> [249.959663] Wrote 50500505, read 00000000, expect 00000000
<6> [249.959664] Wrote 0f0f0f0f, read 00000000, expect 00000000
<6> [249.959665] Wrote f00ff00f, read 00000000, expect 00000000
<6> [249.959666] Wrote 10101010, read 00000000, expect 00000000
<6> [249.959667] Wrote f0f01010, read 00000000, expect 00000000
<6> [249.959668] Wrote 30303030, read 00000000, expect 00000000
<6> [249.959669] Wrote a0a03030, read 00000000, expect 00000000
<6> [249.959670] Wrote 50505050, read 00000000, expect 00000000
<6> [249.959671] Wrote c0c05050, read 00000000, expect 00000000
<6> [249.959672] Wrote f0f0f0f0, read 00000000, expect 00000000
<6> [249.959673] Wrote 11111111, read 00000000, expect 00000000
<6> [249.959674] Wrote 33333333, read 00000000, expect 00000000
<6> [249.959675] Wrote 55555555, read 00000000, expect 00000000
<6> [249.959676] Wrote 0000ffff, read 00000000, expect 00000000
<6> [249.959677] Wrote 00ff00ff, read 00000000, expect 00000000
<6> [249.959678] Wrote ff0000ff, read 00000000, expect 00000000
<6> [249.959679] Wrote ffff00ff, read 00000000, expect 00000000
<6> [249.959679] Wrote ffffffff, read 00000000, expect 00000000
<6> [249.959680] Wrote ffffffff, read 00000000, expect 00000000
<6> [249.959681] Wrote fefefefe, read 00000000, expect 00000000
<6> [249.959682] Wrote efeffefe, read 00000000, expect 00000000
<6> [249.959683] Wrote fcfcfcfc, read 00000000, expect 00000000
<6> [249.959684] Wrote cfcffcfc, read 00000000, expect 00000000
<6> [249.959685] Wrote fafafafa, read 00000000, expect 00000000
<6> [249.959686] Wrote afaffafa, read 00000000, expect 00000000
<6> [249.959687] Wrote f0f0f0f0, read 00000000, expect 00000000
<6> [249.959688] Wrote 0ff00ff0, read 00000000, expect 00000000
<6> [249.959689] Wrote efefefef, read 00000000, expect 00000000
<6> [249.959690] Wrote 0f0fefef, read 00000000, expect 00000000
<6> [249.959691] Wrote cfcfcfcf, read 00000000, expect 00000000
<6> [249.959692] Wrote 5f5fcfcf, read 00000000, expect 00000000
<6> [249.959693] Wrote afafafaf, read 00000000, expect 00000000
<6> [249.959694] Wrote 3f3fafaf, read 00000000, expect 00000000
<6> [249.959695] Wrote 0f0f0f0f, read 00000000, expect 00000000
<6> [249.959696] Wrote eeeeeeee, read 00000000, expect 00000000
<6> [249.959696] Wrote cccccccc, read 00000000, expect 00000000
<6> [249.959697] Wrote aaaaaaaa, read 00000000, expect 00000000
<6> [249.959698] Wrote ffff0000, read 00000000, expect 00000000
<6> [249.959699] Wrote ff00ff00, read 00000000, expect 00000000
<6> [249.959700] Wrote 00ffff00, read 00000000, expect 00000000
<6> [249.959701] Wrote 0000ff00, read 00000000, expect 00000000
<6> [249.959702] Wrote 00000000, read 00000000, expect 00000000

Next plan was to do mmio writes then SRM.

I think someone should tell them it's actually a R/O register now ;)
And we just have to update the test to ignore the lies.
-Chris