Message ID | 20190821063236.19705-1-animesh.manna@intel.com (mailing list archive) |
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Headers | show
Return-Path: <SRS0=ZzEh=WR=lists.freedesktop.org=intel-gfx-bounces@kernel.org> Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 7D59213A4 for <patchwork-intel-gfx@patchwork.kernel.org>; Wed, 21 Aug 2019 06:40:01 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 65764206BA for <patchwork-intel-gfx@patchwork.kernel.org>; Wed, 21 Aug 2019 06:40:01 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 65764206BA Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 5EA656E905; Wed, 21 Aug 2019 06:40:00 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by gabe.freedesktop.org (Postfix) with ESMTPS id 602CA6E908 for <intel-gfx@lists.freedesktop.org>; Wed, 21 Aug 2019 06:39:58 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by fmsmga102.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 20 Aug 2019 23:39:58 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.64,411,1559545200"; d="scan'208";a="195935540" Received: from amanna.iind.intel.com ([10.223.74.216]) by fmsmga001.fm.intel.com with ESMTP; 20 Aug 2019 23:39:54 -0700 From: Animesh Manna <animesh.manna@intel.com> To: intel-gfx@lists.freedesktop.org Date: Wed, 21 Aug 2019 12:02:20 +0530 Message-Id: <20190821063236.19705-1-animesh.manna@intel.com> X-Mailer: git-send-email 2.22.0 MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH v2 00/15] DSB enablement. X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development <intel-gfx.lists.freedesktop.org> List-Unsubscribe: <https://lists.freedesktop.org/mailman/options/intel-gfx>, <mailto:intel-gfx-request@lists.freedesktop.org?subject=unsubscribe> List-Archive: <https://lists.freedesktop.org/archives/intel-gfx> List-Post: <mailto:intel-gfx@lists.freedesktop.org> List-Help: <mailto:intel-gfx-request@lists.freedesktop.org?subject=help> List-Subscribe: <https://lists.freedesktop.org/mailman/listinfo/intel-gfx>, <mailto:intel-gfx-request@lists.freedesktop.org?subject=subscribe> Cc: Jani Nikula <jani.nikula@intel.com>, Lucas De Marchi <lucas.demarchi@intel.com>, Michel Thierry <michel.thierry@intel.com> Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" <intel-gfx-bounces@lists.freedesktop.org> |
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DSB enablement.
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Display State Buffer (DSB) is hardware capability which allows driver to batch submit HW programming. As part of initial enablement common api created which currently used to program gamma lut proramming. Going forwad DSB support can be added for HDR and flip related operation. HSDES: 1209978241 BSpec: 32020 v1: Initial version. v2: Move intel_dsb files under display folder and fixed an issue. Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Cc: Jani Nikula <jani.nikula@intel.com> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Cc: Daniel Vetter <daniel@ffwll.ch> Cc: Imre Deak <imre.deak@intel.com> Cc: Michel Thierry <michel.thierry@intel.com> Cc: Uma Shankar <uma.shankar@intel.com> Cc: Shashank Sharma <shashank.sharma@intel.com> Cc: Swati Sharma <swati2.sharma@intel.com> Cc: Lucas De Marchi <lucas.demarchi@intel.com> Signed-off-by: Animesh Manna <animesh.manna@intel.com> Animesh Manna (15): drm/i915/dsb: feature flag added for display state buffer. drm/i915/dsb: DSB context creation. drm/i915/dsb: single register write function for DSB. drm/i915/dsb: Added enum for reg write capability. drm/i915/dsb: Indexed register write function for DSB. drm/i915/dsb: Update i915_write to call dsb-write. drm/i915/dsb: Register definition of DSB registers. drm/i915/dsb: Check DSB engine status. drm/i915/dsb: functions to enable/disable DSB engine. drm/i915/dsb: function to trigger workload execution of DSB. drm/i915/dsb: function to destroy DSB context. drm/i915/dsb: Early prepare of dsb context. drm/i915/dsb: Cleanup of DSB context. drm/i915/dsb: Documentation for DSB. drm/i915/dsb: Enable gamma lut programming using DSB. Documentation/gpu/i915.rst | 9 + drivers/gpu/drm/i915/Makefile | 1 + drivers/gpu/drm/i915/display/intel_color.c | 4 + drivers/gpu/drm/i915/display/intel_display.c | 27 ++ .../drm/i915/display/intel_display_types.h | 6 + drivers/gpu/drm/i915/display/intel_dsb.c | 313 ++++++++++++++++++ drivers/gpu/drm/i915/display/intel_dsb.h | 48 +++ drivers/gpu/drm/i915/i915_drv.h | 9 +- drivers/gpu/drm/i915/i915_reg.h | 53 ++- drivers/gpu/drm/i915/intel_device_info.h | 1 + 10 files changed, 461 insertions(+), 10 deletions(-) create mode 100644 drivers/gpu/drm/i915/display/intel_dsb.c create mode 100644 drivers/gpu/drm/i915/display/intel_dsb.h