Message ID | 20190827191026.26175-1-animesh.manna@intel.com (mailing list archive) |
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Headers | show
Return-Path: <SRS0=vzYQ=WX=lists.freedesktop.org=intel-gfx-bounces@kernel.org> Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 7C87A14F7 for <patchwork-intel-gfx@patchwork.kernel.org>; Tue, 27 Aug 2019 19:17:59 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 67FA02184D for <patchwork-intel-gfx@patchwork.kernel.org>; Tue, 27 Aug 2019 19:17:59 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 67FA02184D Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id CFA7489B65; Tue, 27 Aug 2019 19:17:58 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by gabe.freedesktop.org (Postfix) with ESMTPS id 3FD3B89B69 for <intel-gfx@lists.freedesktop.org>; Tue, 27 Aug 2019 19:17:57 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by orsmga101.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 27 Aug 2019 12:17:56 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.64,438,1559545200"; d="scan'208";a="209863339" Received: from amanna.iind.intel.com ([10.223.74.216]) by fmsmga002.fm.intel.com with ESMTP; 27 Aug 2019 12:17:52 -0700 From: Animesh Manna <animesh.manna@intel.com> To: intel-gfx@lists.freedesktop.org Date: Wed, 28 Aug 2019 00:40:14 +0530 Message-Id: <20190827191026.26175-1-animesh.manna@intel.com> X-Mailer: git-send-email 2.22.0 MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH v3 00/11] DSB enablement. X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development <intel-gfx.lists.freedesktop.org> List-Unsubscribe: <https://lists.freedesktop.org/mailman/options/intel-gfx>, <mailto:intel-gfx-request@lists.freedesktop.org?subject=unsubscribe> List-Archive: <https://lists.freedesktop.org/archives/intel-gfx> List-Post: <mailto:intel-gfx@lists.freedesktop.org> List-Help: <mailto:intel-gfx-request@lists.freedesktop.org?subject=help> List-Subscribe: <https://lists.freedesktop.org/mailman/listinfo/intel-gfx>, <mailto:intel-gfx-request@lists.freedesktop.org?subject=subscribe> Cc: Jani Nikula <jani.nikula@intel.com>, Lucas De Marchi <lucas.demarchi@intel.com>, Michel Thierry <michel.thierry@intel.com> Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" <intel-gfx-bounces@lists.freedesktop.org> |
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DSB enablement.
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Display State Buffer (DSB) is hardware capability which allows driver to batch submit HW programming. As part of initial enablement common api created which currently used to program gamma lut proramming. Going forwad DSB support can be added for HDR and flip related operation. HSDES: 1209978241 BSpec: 32020 v1: Initial version. v2: Move intel_dsb files under display folder and fixed an issue. v3: As per review comments from Chris and Jani, - removed some unwanted code. (Chris) - Used i915_gem_object_create_internal instead of _shmem. (Chris) - cmd_buf_tail removed and can be derived through vma object. (Chris) - Simplified and optimized code few places. (Chris) - Called dsb-api directly in callsites instead going via I915_WRITE. (Jani) Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Cc: Jani Nikula <jani.nikula@intel.com> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Cc: Daniel Vetter <daniel@ffwll.ch> Cc: Imre Deak <imre.deak@intel.com> Cc: Michel Thierry <michel.thierry@intel.com> Cc: Uma Shankar <uma.shankar@intel.com> Cc: Shashank Sharma <shashank.sharma@intel.com> Cc: Swati Sharma <swati2.sharma@intel.com> Cc: Lucas De Marchi <lucas.demarchi@intel.com> Signed-off-by: Animesh Manna <animesh.manna@intel.com> Animesh Manna (11): drm/i915/dsb: feature flag added for display state buffer. drm/i915/dsb: DSB context creation. drm/i915/dsb: single register write function for DSB. drm/i915/dsb: Indexed register write function for DSB. drm/i915/dsb: Register definition of DSB registers. drm/i915/dsb: Check DSB engine status. drm/i915/dsb: functions to enable/disable DSB engine. drm/i915/dsb: function to trigger workload execution of DSB. drm/i915/dsb: Documentation for DSB. drm/i915/dsb: Enable gamma lut programming using DSB. drm/i915/dsb: Enable DSB for gen12. Documentation/gpu/i915.rst | 9 + drivers/gpu/drm/i915/Makefile | 1 + drivers/gpu/drm/i915/display/intel_color.c | 64 ++-- .../drm/i915/display/intel_display_types.h | 3 + drivers/gpu/drm/i915/display/intel_dsb.c | 326 ++++++++++++++++++ drivers/gpu/drm/i915/display/intel_dsb.h | 49 +++ drivers/gpu/drm/i915/i915_drv.h | 5 + drivers/gpu/drm/i915/i915_pci.c | 3 +- drivers/gpu/drm/i915/i915_reg.h | 15 + drivers/gpu/drm/i915/intel_device_info.h | 1 + 10 files changed, 452 insertions(+), 24 deletions(-) create mode 100644 drivers/gpu/drm/i915/display/intel_dsb.c create mode 100644 drivers/gpu/drm/i915/display/intel_dsb.h