| Message ID | 20190909034325.20006-1-manasi.d.navare@intel.com (mailing list archive) |
|---|---|
| Headers | show |
| Series | Remaining patches to enable Transcoder Port Sync for tiled displays | expand |
On Sun, 08 Sep 2019, Manasi Navare <manasi.d.navare@intel.com> wrote: > This patch series addresses all review comments and now the enable and > disable paths follow the method of obtaining slave states from master > and updating master-slaves in correct order during master modeset. Main high level question: what does it take to enable this on gen9+? BR, Jani.
On Tue, Sep 10, 2019 at 12:29:19PM +0300, Jani Nikula wrote: > On Sun, 08 Sep 2019, Manasi Navare <manasi.d.navare@intel.com> wrote: > > This patch series addresses all review comments and now the enable and > > disable paths follow the method of obtaining slave states from master > > and updating master-slaves in correct order during master modeset. > > Main high level question: what does it take to enable this on gen9+? As per the Bspec project platforms, the first platform that supports this is ICL Regards Manasi > > BR, > Jani. > > > -- > Jani Nikula, Intel Open Source Graphics Center
On Tue, Sep 10, 2019 at 11:07:30AM -0700, Manasi Navare wrote: > On Tue, Sep 10, 2019 at 12:29:19PM +0300, Jani Nikula wrote: > > On Sun, 08 Sep 2019, Manasi Navare <manasi.d.navare@intel.com> wrote: > > > This patch series addresses all review comments and now the enable and > > > disable paths follow the method of obtaining slave states from master > > > and updating master-slaves in correct order during master modeset. > > > > Main high level question: what does it take to enable this on gen9+? > > As per the Bspec project platforms, the first platform that supports this is > ICL Hi Jani, Apparently the Bspec caused some confusion, after double checking with the HW teams here, this feature is enabled starting BDW for the SST connectors and only the MST support is new to Gen 11+. So i guess I can change the patches to add support starting BDW and this should also fix the 5K tiled display issue that Ankit has been working on Manasi > > Regards > Manasi > > > > > BR, > > Jani. > > > > > > -- > > Jani Nikula, Intel Open Source Graphics Center > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
On Tue, 10 Sep 2019, Manasi Navare <manasi.d.navare@intel.com> wrote: > On Tue, Sep 10, 2019 at 11:07:30AM -0700, Manasi Navare wrote: >> On Tue, Sep 10, 2019 at 12:29:19PM +0300, Jani Nikula wrote: >> > On Sun, 08 Sep 2019, Manasi Navare <manasi.d.navare@intel.com> wrote: >> > > This patch series addresses all review comments and now the enable and >> > > disable paths follow the method of obtaining slave states from master >> > > and updating master-slaves in correct order during master modeset. >> > >> > Main high level question: what does it take to enable this on gen9+? >> >> As per the Bspec project platforms, the first platform that supports this is >> ICL > > Hi Jani, > > Apparently the Bspec caused some confusion, after double checking with the > HW teams here, this feature is enabled starting BDW for the SST connectors > and only the MST support is new to Gen 11+. > > So i guess I can change the patches to add support starting BDW and > this should also fix the 5K tiled display issue that Ankit has been > working on Thanks! I don't mind getting the patches merged for ICL+ at first, and updating to cover older gens in follow-up. BR, Jani. > > Manasi > >> >> Regards >> Manasi >> >> > >> > BR, >> > Jani. >> > >> > >> > -- >> > Jani Nikula, Intel Open Source Graphics Center >> _______________________________________________ >> Intel-gfx mailing list >> Intel-gfx@lists.freedesktop.org >> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
On Wed, Sep 11, 2019 at 12:08:00PM +0300, Jani Nikula wrote: > On Tue, 10 Sep 2019, Manasi Navare <manasi.d.navare@intel.com> wrote: > > On Tue, Sep 10, 2019 at 11:07:30AM -0700, Manasi Navare wrote: > >> On Tue, Sep 10, 2019 at 12:29:19PM +0300, Jani Nikula wrote: > >> > On Sun, 08 Sep 2019, Manasi Navare <manasi.d.navare@intel.com> wrote: > >> > > This patch series addresses all review comments and now the enable and > >> > > disable paths follow the method of obtaining slave states from master > >> > > and updating master-slaves in correct order during master modeset. > >> > > >> > Main high level question: what does it take to enable this on gen9+? > >> > >> As per the Bspec project platforms, the first platform that supports this is > >> ICL > > > > Hi Jani, > > > > Apparently the Bspec caused some confusion, after double checking with the > > HW teams here, this feature is enabled starting BDW for the SST connectors > > and only the MST support is new to Gen 11+. > > > > So i guess I can change the patches to add support starting BDW and > > this should also fix the 5K tiled display issue that Ankit has been > > working on > > Thanks! I don't mind getting the patches merged for ICL+ at first, and > updating to cover older gens in follow-up. So you are suggesting that i keep the patches as is and have them get merged first and then i could change the GEN checks to add support for BDW+? Regards Manasi > > BR, > Jani. > > > > > > Manasi > > > >> > >> Regards > >> Manasi > >> > >> > > >> > BR, > >> > Jani. > >> > > >> > > >> > -- > >> > Jani Nikula, Intel Open Source Graphics Center > >> _______________________________________________ > >> Intel-gfx mailing list > >> Intel-gfx@lists.freedesktop.org > >> https://lists.freedesktop.org/mailman/listinfo/intel-gfx > > -- > Jani Nikula, Intel Open Source Graphics Center
On Wed, 11 Sep 2019, Manasi Navare <manasi.d.navare@intel.com> wrote: > On Wed, Sep 11, 2019 at 12:08:00PM +0300, Jani Nikula wrote: >> On Tue, 10 Sep 2019, Manasi Navare <manasi.d.navare@intel.com> wrote: >> > On Tue, Sep 10, 2019 at 11:07:30AM -0700, Manasi Navare wrote: >> >> On Tue, Sep 10, 2019 at 12:29:19PM +0300, Jani Nikula wrote: >> >> > On Sun, 08 Sep 2019, Manasi Navare <manasi.d.navare@intel.com> wrote: >> >> > > This patch series addresses all review comments and now the enable and >> >> > > disable paths follow the method of obtaining slave states from master >> >> > > and updating master-slaves in correct order during master modeset. >> >> > >> >> > Main high level question: what does it take to enable this on gen9+? >> >> >> >> As per the Bspec project platforms, the first platform that supports this is >> >> ICL >> > >> > Hi Jani, >> > >> > Apparently the Bspec caused some confusion, after double checking with the >> > HW teams here, this feature is enabled starting BDW for the SST connectors >> > and only the MST support is new to Gen 11+. >> > >> > So i guess I can change the patches to add support starting BDW and >> > this should also fix the 5K tiled display issue that Ankit has been >> > working on >> >> Thanks! I don't mind getting the patches merged for ICL+ at first, and >> updating to cover older gens in follow-up. > > So you are suggesting that i keep the patches as is and have them get > merged first and then i could change the GEN checks to add support for > BDW+? I'm saying it's up to you. Whatever makes most sense to you. If you're at the brink of getting the ICL patches merged, there's not much point in rehashing and delaying that, is there? BR, Jani. > > Regards > Manasi > >> >> BR, >> Jani. >> >> >> > >> > Manasi >> > >> >> >> >> Regards >> >> Manasi >> >> >> >> > >> >> > BR, >> >> > Jani. >> >> > >> >> > >> >> > -- >> >> > Jani Nikula, Intel Open Source Graphics Center >> >> _______________________________________________ >> >> Intel-gfx mailing list >> >> Intel-gfx@lists.freedesktop.org >> >> https://lists.freedesktop.org/mailman/listinfo/intel-gfx >> >> -- >> Jani Nikula, Intel Open Source Graphics Center
On Thu, Sep 12, 2019 at 09:42:11AM +0300, Jani Nikula wrote: > On Wed, 11 Sep 2019, Manasi Navare <manasi.d.navare@intel.com> wrote: > > On Wed, Sep 11, 2019 at 12:08:00PM +0300, Jani Nikula wrote: > >> On Tue, 10 Sep 2019, Manasi Navare <manasi.d.navare@intel.com> wrote: > >> > On Tue, Sep 10, 2019 at 11:07:30AM -0700, Manasi Navare wrote: > >> >> On Tue, Sep 10, 2019 at 12:29:19PM +0300, Jani Nikula wrote: > >> >> > On Sun, 08 Sep 2019, Manasi Navare <manasi.d.navare@intel.com> wrote: > >> >> > > This patch series addresses all review comments and now the enable and > >> >> > > disable paths follow the method of obtaining slave states from master > >> >> > > and updating master-slaves in correct order during master modeset. > >> >> > > >> >> > Main high level question: what does it take to enable this on gen9+? > >> >> > >> >> As per the Bspec project platforms, the first platform that supports this is > >> >> ICL > >> > > >> > Hi Jani, > >> > > >> > Apparently the Bspec caused some confusion, after double checking with the > >> > HW teams here, this feature is enabled starting BDW for the SST connectors > >> > and only the MST support is new to Gen 11+. > >> > > >> > So i guess I can change the patches to add support starting BDW and > >> > this should also fix the 5K tiled display issue that Ankit has been > >> > working on > >> > >> Thanks! I don't mind getting the patches merged for ICL+ at first, and > >> updating to cover older gens in follow-up. > > > > So you are suggesting that i keep the patches as is and have them get > > merged first and then i could change the GEN checks to add support for > > BDW+? > > I'm saying it's up to you. Whatever makes most sense to you. If you're > at the brink of getting the ICL patches merged, there's not much point > in rehashing and delaying that, is there? Yes I agree, thanks a lot Jani for your inputs/suggestions. I will push for the reviews on these for ICL+ and get these merged first. Manasi > > BR, > Jani. > > > > > > Regards > > Manasi > > > >> > >> BR, > >> Jani. > >> > >> > >> > > >> > Manasi > >> > > >> >> > >> >> Regards > >> >> Manasi > >> >> > >> >> > > >> >> > BR, > >> >> > Jani. > >> >> > > >> >> > > >> >> > -- > >> >> > Jani Nikula, Intel Open Source Graphics Center > >> >> _______________________________________________ > >> >> Intel-gfx mailing list > >> >> Intel-gfx@lists.freedesktop.org > >> >> https://lists.freedesktop.org/mailman/listinfo/intel-gfx > >> > >> -- > >> Jani Nikula, Intel Open Source Graphics Center > > -- > Jani Nikula, Intel Open Source Graphics Center
This patch series addresses all review comments and now the enable and disable paths follow the method of obtaining slave states from master and updating master-slaves in correct order during master modeset. The ddb allocations and watermarks changes are not addressed here and will be added after the basic support gets upstreamed Manasi Navare (6): drm/i915/display/icl: Save Master transcoder in slave's crtc_state for Transcoder Port Sync drm/i915/display/icl: Enable TRANSCODER PORT SYNC for tiled displays across separate ports drm/i915/display/icl: HW state readout for transcoder port sync config drm/i915/display/icl: Enable master-slaves in trans port sync drm/i915/display/icl: Disable transcoder port sync as part of crtc_disable() sequence drm/i915/display/icl: In port sync mode disable slaves first then master drivers/gpu/drm/i915/display/intel_ddi.c | 3 +- drivers/gpu/drm/i915/display/intel_display.c | 438 +++++++++++++++++- drivers/gpu/drm/i915/display/intel_display.h | 5 + .../drm/i915/display/intel_display_types.h | 6 + 4 files changed, 443 insertions(+), 9 deletions(-)