[v2,0/2] Re-enable FBC on TGL

Message ID	20201119155050.20328-1-uma.shankar@intel.com (mailing list archive)
Headers	show Return-Path: <SRS0=vAY1=EZ=lists.freedesktop.org=intel-gfx-bounces@kernel.org> DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org D3F6C22202 IronPort-SDR: BTB5Scr0fyAOBpaoalqLCAmFVs3aWHBlObcupMgKAtyNkAcYJA7ivaoX+yYlaQZt8/NZrOEIrb slU1OrY0TD7A== IronPort-SDR: OylgnAhwAMbcZNgEAkTLyO94GHBBbzRiiTHIrFdYk3pxFBLvDw4Ww3wGGheu+VdGMbr/gmGac6 lKKqMuArHZ5w== From: Uma Shankar <uma.shankar@intel.com> To: intel-gfx@lists.freedesktop.org Date: Thu, 19 Nov 2020 21:20:48 +0530 Message-Id: <20201119155050.20328-1-uma.shankar@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [v2 0/2] Re-enable FBC on TGL Precedence: list Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" <intel-gfx-bounces@lists.freedesktop.org>
Series	Re-enable FBC on TGL \| expand [v2,0/2] Re-enable FBC on TGL [v2,1/2] drm/i915/display/tgl: Disable FBC with PSR2 [v2,2/2] Revert "drm/i915/display/fbc: Disable fbc by default on TGL"

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20201119155050.20328-1-uma.shankar@intel.com (mailing list archive)

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From: Uma Shankar <uma.shankar@intel.com>
To: intel-gfx@lists.freedesktop.org
Date: Thu, 19 Nov 2020 21:20:48 +0530
Message-Id: <20201119155050.20328-1-uma.shankar@intel.com>
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Subject: [Intel-gfx] [v2 0/2] Re-enable FBC on TGL
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Series

Re-enable FBC on TGL | expand

Message

Shankar, Uma Nov. 19, 2020, 3:50 p.m. UTC

FBC was disabled on TGL due to random underruns. It has
been determined that FBC will not work reliably with PSR2.
This series re-enables fbc along with taking care of the
PSR2 limitations for TGL.

Bspec: 50422 HSD: 14010260002

v2: Addressed review comments and added bspec links

Uma Shankar (2):
  drm/i915/display/tgl: Disable FBC with PSR2
  Revert "drm/i915/display/fbc: Disable fbc by default on TGL"

 drivers/gpu/drm/i915/display/intel_fbc.c | 18 +++++++++++-------
 1 file changed, 11 insertions(+), 7 deletions(-)