From patchwork Thu Mar 11 22:35:36 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Matt Roper X-Patchwork-Id: 12133027 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-11.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE, SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6CB12C433DB for ; Thu, 11 Mar 2021 22:36:50 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 32CF764F26 for ; Thu, 11 Mar 2021 22:36:50 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 32CF764F26 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id B10796EE96; Thu, 11 Mar 2021 22:36:47 +0000 (UTC) Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by gabe.freedesktop.org (Postfix) with ESMTPS id 78BF66EE84 for ; Thu, 11 Mar 2021 22:36:46 +0000 (UTC) IronPort-SDR: ayMM1hgDijsGELNJ/TaIhLASSYfSqxMmMeZWgv6RBdANxlmyfOF9vl3BCLWKTdIU7EqEETkmOt 3jadsNDHrW/Q== X-IronPort-AV: E=McAfee;i="6000,8403,9920"; a="185395066" X-IronPort-AV: E=Sophos;i="5.81,241,1610438400"; d="scan'208";a="185395066" Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 Mar 2021 14:36:44 -0800 IronPort-SDR: or0g4DiW90CQySLN9o6Wr39aretGi3CXC+f8Tg0oBVNziJQxKtjiLU9/X8r1HI4FZKlwSIOyhH aF09bpAhsVKg== X-IronPort-AV: E=Sophos;i="5.81,241,1610438400"; d="scan'208";a="438852656" Received: from mdroper-desk1.fm.intel.com ([10.1.27.168]) by fmsmga003-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 Mar 2021 14:36:43 -0800 From: Matt Roper To: intel-gfx@lists.freedesktop.org Date: Thu, 11 Mar 2021 14:35:36 -0800 Message-Id: <20210311223632.3191939-1-matthew.d.roper@intel.com> X-Mailer: git-send-email 2.25.4 MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 00/56] Introduce Alder Lake-P X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" This series introduces Alder Lake-P (ADL-P). ADL-P is our first platform to utilize the new XE_LPD display architecture (version 13 of that IP block). The graphics and media IP blocks remain at version 12 of their respective architectures, so there are relatively few i915 changes needed outside of the display code. The first 23 patches in this series are a just repeat of the general XE_LPD support and refactoring that I posted (and explained in more depth) in this series: https://patchwork.freedesktop.org/series/87886/ The remaining 33 patches provide the changes that are specific to the ADL-P platform. Most of preparation of this patch series was done by Clint Taylor, and he'll be the main point of contact for shepherding the ADL-P patches upstream. Cc: Clinton Taylor Animesh Manna (3): drm/i915/bigjoiner: Mode validation with uncompressed pipe joiner drm/i915/bigjoiner: Avoid dsc_compute_config for uncompressed bigjoiner drm/i915/bigjoiner: atomic commit changes for uncompressed joiner Anusha Srivatsa (7): drm/i915/adl_p: Load DMC drm/i915/adl_p: Setup ports/phys drm/i915/adl_p: Add cdclk support for ADL-P drm/i915/adl_p: Add initial ADL_P Workarounds drm/i915/adl_p: Add PLL Support drm/i915/adlp: Add PIPE_MISC2 programming drm/i915/adl_p: Update memory bandwidth parameters Clint Taylor (1): drm/i915/adlp: Define GuC/HuC for Alderlake_P Clinton Taylor (3): drm/i915/adl_p: Add PCI Devices IDs drm/i915/adl_p: ADL_P device info enabling drm/i915/adl_p: Add PCH support José Roberto de Souza (9): drm/i915/display/tc: Rename safe_mode functions ownership drm/i915/adl_p: Handle TC cold drm/i915/adl_p: Implement TC sequences drm/i915/adl_p: Enable modular fia drm/i915/adl_p: Don't config MBUS and DBUF during display initialization drm/i915/adl_p: Implement Wa_22011091694 drm/i915/display/adl_p: Implement Wa_22011320316 drm/i915/display/adl_p: Remove CCS support drm/i915/display/adl_p: Implement PSR changes Juha-Pekka Heikkilä (1): drm/i915/xelpd: Support 128k plane stride Manasi Navare (1): drm/i915/xelpd: Add VRR guardband for VRR CTL Matt Roper (17): drm/i915/display: Convert gen5/gen6 tests to IS_IRONLAKE/IS_SANDYBRIDGE drm/i915: Add DISPLAY_VER() drm/i915/display: Eliminate most usage of INTEL_GEN() drm/i915: Convert INTEL_GEN() to DISPLAY_VER() as appropriate in intel_pm.c drm/i915: Convert INTEL_GEN() to DISPLAY_VER() as appropriate in i915_irq.c drm/i915/display: Simplify GLK display version tests drm/i915/xelpd: add XE_LPD display characteristics drm/i915/xelpd: Handle proper AUX interrupt bits drm/i915/xelpd: Enhanced pipe underrun reporting drm/i915/xelpd: Define plane capabilities drm/i915/xelpd: Handle new location of outputs D and E drm/i915/xelpd: Add XE_LPD power wells drm/i915/xelpd: Increase maximum watermark lines to 255 drm/i915/xelpd: Required bandwidth increases when VT-d is active drm/i915/xelpd: Add Wa_14011503030 drm/i915/adl_p: Add dedicated SAGV watermarks drm/i915/adl_p: Extend PLANE_WM bits for blocks & lines Mika Kahola (3): drm/i915/adl_p: Tx escape clock with DSI drm/i915/adl_p: Define and use ADL-P specific DP translation tables drm/i915/adl_p: Enable/disable loadgen sharing Uma Shankar (1): drm/i915/xelpd: Handle LPSP for XE_LPD Umesh Nerlige Ramappa (1): drm/i915/perf: Enable OA formats for ADL_P Vandita Kulkarni (7): drm/i915/display/dsc: Refactor intel_dp_dsc_compute_bpp drm/i915/xelpd: Support DP1.4 compression BPPs drm/i915: Get slice height before computing rc params drm/i915/xelpd: Calculate VDSC RC parameters drm/i915/xelpd: Add rc_qp_table for rcparams calculation drm/i915/adl_p: Add ddb allocation support drm/i915/adl_p: MBUS programming Ville Syrjälä (2): drm/i915: Introduce MBUS relative dbuf offsets drm/i915: Move intel_modeset_all_pipes() arch/x86/kernel/early-quirks.c | 1 + drivers/gpu/drm/i915/display/i9xx_plane.c | 56 +- drivers/gpu/drm/i915/display/icl_dsi.c | 35 +- drivers/gpu/drm/i915/display/intel_atomic.c | 27 +- drivers/gpu/drm/i915/display/intel_atomic.h | 1 + drivers/gpu/drm/i915/display/intel_audio.c | 18 +- drivers/gpu/drm/i915/display/intel_bios.c | 24 +- drivers/gpu/drm/i915/display/intel_bw.c | 15 +- drivers/gpu/drm/i915/display/intel_cdclk.c | 152 +++--- drivers/gpu/drm/i915/display/intel_color.c | 32 +- .../gpu/drm/i915/display/intel_combo_phy.c | 8 +- drivers/gpu/drm/i915/display/intel_crt.c | 12 +- drivers/gpu/drm/i915/display/intel_crtc.c | 20 +- drivers/gpu/drm/i915/display/intel_csr.c | 14 +- drivers/gpu/drm/i915/display/intel_cursor.c | 14 +- drivers/gpu/drm/i915/display/intel_ddi.c | 144 ++--- .../drm/i915/display/intel_ddi_buf_trans.c | 38 +- .../drm/i915/display/intel_ddi_buf_trans.h | 4 + drivers/gpu/drm/i915/display/intel_display.c | 378 ++++++++----- drivers/gpu/drm/i915/display/intel_display.h | 9 + .../drm/i915/display/intel_display_debugfs.c | 50 +- .../drm/i915/display/intel_display_power.c | 503 +++++++++++++++++- .../drm/i915/display/intel_display_power.h | 11 + .../drm/i915/display/intel_display_types.h | 2 +- drivers/gpu/drm/i915/display/intel_dp.c | 125 +++-- drivers/gpu/drm/i915/display/intel_dp_aux.c | 24 +- drivers/gpu/drm/i915/display/intel_dp_mst.c | 20 +- drivers/gpu/drm/i915/display/intel_dpll.c | 12 +- drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 91 +++- drivers/gpu/drm/i915/display/intel_dsi_vbt.c | 4 +- drivers/gpu/drm/i915/display/intel_fbc.c | 62 +-- drivers/gpu/drm/i915/display/intel_fdi.c | 6 +- .../drm/i915/display/intel_fifo_underrun.c | 73 ++- drivers/gpu/drm/i915/display/intel_gmbus.c | 4 +- drivers/gpu/drm/i915/display/intel_hdcp.c | 11 +- drivers/gpu/drm/i915/display/intel_hdmi.c | 31 +- drivers/gpu/drm/i915/display/intel_lvds.c | 12 +- drivers/gpu/drm/i915/display/intel_overlay.c | 12 +- drivers/gpu/drm/i915/display/intel_panel.c | 18 +- drivers/gpu/drm/i915/display/intel_pipe_crc.c | 16 +- drivers/gpu/drm/i915/display/intel_pps.c | 6 +- drivers/gpu/drm/i915/display/intel_psr.c | 98 ++-- .../gpu/drm/i915/display/intel_qp_tables.c | 272 ++++++++++ .../gpu/drm/i915/display/intel_qp_tables.h | 34 ++ drivers/gpu/drm/i915/display/intel_sdvo.c | 8 +- drivers/gpu/drm/i915/display/intel_sprite.c | 16 +- drivers/gpu/drm/i915/display/intel_tc.c | 167 +++++- drivers/gpu/drm/i915/display/intel_tv.c | 8 +- drivers/gpu/drm/i915/display/intel_vdsc.c | 166 +++++- drivers/gpu/drm/i915/display/intel_vdsc.h | 2 + drivers/gpu/drm/i915/display/intel_vga.c | 4 +- drivers/gpu/drm/i915/display/intel_vrr.c | 56 +- drivers/gpu/drm/i915/display/skl_scaler.c | 8 +- .../drm/i915/display/skl_universal_plane.c | 145 +++-- drivers/gpu/drm/i915/gt/gen8_engine_cs.c | 4 +- drivers/gpu/drm/i915/gt/intel_workarounds.c | 59 +- drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 1 + drivers/gpu/drm/i915/i915_drv.h | 16 + drivers/gpu/drm/i915/i915_irq.c | 92 ++-- drivers/gpu/drm/i915/i915_pci.c | 26 +- drivers/gpu/drm/i915/i915_perf.c | 1 + drivers/gpu/drm/i915/i915_reg.h | 204 +++++-- drivers/gpu/drm/i915/intel_device_info.c | 3 +- drivers/gpu/drm/i915/intel_device_info.h | 4 + drivers/gpu/drm/i915/intel_pch.c | 6 +- drivers/gpu/drm/i915/intel_pch.h | 1 + drivers/gpu/drm/i915/intel_pm.c | 465 +++++++++++++--- drivers/gpu/drm/i915/intel_pm.h | 2 +- include/drm/i915_pciids.h | 20 + 69 files changed, 2990 insertions(+), 993 deletions(-) create mode 100644 drivers/gpu/drm/i915/display/intel_qp_tables.c create mode 100644 drivers/gpu/drm/i915/display/intel_qp_tables.h