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[0/6] Enable WAs related to DG2

Message ID 20220415224025.3693037-1-umesh.nerlige.ramappa@intel.com (mailing list archive)
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Series Enable WAs related to DG2 | expand

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Umesh Nerlige Ramappa April 15, 2022, 10:40 p.m. UTC 
Enable work arounds related to DG2.

Signed-off-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
Signed-off-by: Vinay Belgaumkar <vinay.belgaumkar@intel.com>
Signed-off-by: Tilak Tangudu <tilak.tangudu@intel.com>
Signed-off-by: Matthew Brost <matthew.brost@intel.com>

John Harrison (2):
  drm/i915/guc: Enable GuC based workarounds for DG2
  drm/i915/dg2: Enable Wa_22012727170/Wa_22012727685

Matthew Brost (1):
  drm/i915/dg2: Enable Wa_14014475959 - RCS / CCS context exit

Tilak Tangudu (1):
  drm/i915: Add Wa_22011802037 force cs halt

Umesh Nerlige Ramappa (1):
  drm/i915/guc: Enable Wa_22011802037 for gen12 GuC based platforms

Vinay Belgaumkar (1):
  drm/i915/guc: Apply Wa_16011777198

 drivers/gpu/drm/i915/gt/gen8_engine_cs.c      | 41 +++++++++
 drivers/gpu/drm/i915/gt/intel_engine_cs.c     |  9 ++
 drivers/gpu/drm/i915/gt/intel_engine_regs.h   |  1 +
 drivers/gpu/drm/i915/gt/intel_engine_types.h  |  8 ++
 drivers/gpu/drm/i915/gt/intel_gpu_commands.h  |  7 ++
 drivers/gpu/drm/i915/gt/intel_gt_pm.c         |  9 +-
 drivers/gpu/drm/i915/gt/intel_gt_regs.h       | 18 ++++
 drivers/gpu/drm/i915/gt/intel_reset.c         |  5 +-
 drivers/gpu/drm/i915/gt/uc/intel_guc.c        | 35 ++++++++
 drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h   |  8 +-
 .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 89 ++++++++++++++++++-
 11 files changed, 222 insertions(+), 8 deletions(-)