| Message ID | 20220520230408.3787166-1-matthew.d.roper@intel.com (mailing list archive) |
|---|---|
| Headers | show |
| Series | i915: SSEU handling updates | expand |
On Mon, May 23, 2022 at 09:23:33PM +0000, Patchwork wrote: > == Series Details == > > Series: i915: SSEU handling updates (rev2) > URL : https://patchwork.freedesktop.org/series/104244/ > State : failure > > == Summary == > > CI Bug Log - changes from CI_DRM_11693 -> Patchwork_104244v2 > ==================================================== > > Summary > ------- > > **FAILURE** > > Serious unknown changes coming with Patchwork_104244v2 absolutely need to be > verified manually. > > If you think the reported changes have nothing to do with the changes > introduced in Patchwork_104244v2, please notify your bug team to allow them > to document this new failure mode, which will reduce false positives in CI. > > External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/index.html > > Participating hosts (44 -> 45) > ------------------------------ > > Additional (2): fi-icl-u2 fi-tgl-u2 > Missing (1): fi-hsw-4770 > > Possible new issues > ------------------- > > Here are the unknown changes that may have been introduced in Patchwork_104244v2: > > ### CI changes ### > > #### Possible regressions #### > > * boot: > - fi-bdw-5557u: [PASS][1] -> [FAIL][2] > [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11693/fi-bdw-5557u/boot.html > [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/fi-bdw-5557u/boot.html I don't see a boot failure here? It looks like i915 loaded successfully, without errors. It also looks like more tests ran successfully on the machine after that as well. Matt > > > Known issues > ------------ > > Here are the changes found in Patchwork_104244v2 that come from known issues: > > ### IGT changes ### > > #### Issues hit #### > > * igt@gem_exec_gttfill@basic: > - fi-icl-u2: NOTRUN -> [INCOMPLETE][3] ([i915#4890]) > [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/fi-icl-u2/igt@gem_exec_gttfill@basic.html > > * igt@gem_huc_copy@huc-copy: > - fi-tgl-u2: NOTRUN -> [SKIP][4] ([i915#2190]) > [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/fi-tgl-u2/igt@gem_huc_copy@huc-copy.html > > * igt@i915_selftest@live@hangcheck: > - bat-dg1-6: [PASS][5] -> [DMESG-FAIL][6] ([i915#4494] / [i915#4957]) > [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11693/bat-dg1-6/igt@i915_selftest@live@hangcheck.html > [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/bat-dg1-6/igt@i915_selftest@live@hangcheck.html > - fi-snb-2600: [PASS][7] -> [INCOMPLETE][8] ([i915#3921]) > [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11693/fi-snb-2600/igt@i915_selftest@live@hangcheck.html > [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/fi-snb-2600/igt@i915_selftest@live@hangcheck.html > > * igt@kms_busy@basic@flip: > - fi-tgl-u2: NOTRUN -> [DMESG-WARN][9] ([i915#402]) +3 similar issues > [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/fi-tgl-u2/igt@kms_busy@basic@flip.html > > * igt@kms_chamelium@dp-hpd-fast: > - fi-tgl-u2: NOTRUN -> [SKIP][10] ([fdo#109284] / [fdo#111827]) +7 similar issues > [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/fi-tgl-u2/igt@kms_chamelium@dp-hpd-fast.html > > * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic: > - fi-tgl-u2: NOTRUN -> [SKIP][11] ([i915#4103]) +1 similar issue > [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/fi-tgl-u2/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html > > * igt@kms_flip@basic-flip-vs-modeset@b-edp1: > - bat-adlp-4: [PASS][12] -> [DMESG-WARN][13] ([i915#3576]) > [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11693/bat-adlp-4/igt@kms_flip@basic-flip-vs-modeset@b-edp1.html > [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/bat-adlp-4/igt@kms_flip@basic-flip-vs-modeset@b-edp1.html > > * igt@kms_force_connector_basic@force-load-detect: > - fi-tgl-u2: NOTRUN -> [SKIP][14] ([fdo#109285]) > [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/fi-tgl-u2/igt@kms_force_connector_basic@force-load-detect.html > > * igt@kms_setmode@basic-clone-single-crtc: > - fi-tgl-u2: NOTRUN -> [SKIP][15] ([i915#3555]) > [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/fi-tgl-u2/igt@kms_setmode@basic-clone-single-crtc.html > > * igt@prime_vgem@basic-userptr: > - fi-tgl-u2: NOTRUN -> [SKIP][16] ([i915#3301]) > [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/fi-tgl-u2/igt@prime_vgem@basic-userptr.html > > * igt@runner@aborted: > - fi-icl-u2: NOTRUN -> [FAIL][17] ([i915#4312]) > [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/fi-icl-u2/igt@runner@aborted.html > > > #### Possible fixes #### > > * igt@gem_exec_suspend@basic-s0@smem: > - {fi-ehl-2}: [DMESG-WARN][18] ([i915#5122]) -> [PASS][19] > [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11693/fi-ehl-2/igt@gem_exec_suspend@basic-s0@smem.html > [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/fi-ehl-2/igt@gem_exec_suspend@basic-s0@smem.html > > * igt@kms_flip@basic-plain-flip@a-edp1: > - bat-adlp-4: [DMESG-WARN][20] ([i915#3576]) -> [PASS][21] +2 similar issues > [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11693/bat-adlp-4/igt@kms_flip@basic-plain-flip@a-edp1.html > [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/bat-adlp-4/igt@kms_flip@basic-plain-flip@a-edp1.html > > > {name}: This element is suppressed. This means it is ignored when computing > the status of the difference (SUCCESS, WARNING, or FAILURE). > > [fdo#109284]: https://bugs.freedesktop.org/show_bug.cgi?id=109284 > [fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285 > [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827 > [i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190 > [i915#3301]: https://gitlab.freedesktop.org/drm/intel/issues/3301 > [i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555 > [i915#3576]: https://gitlab.freedesktop.org/drm/intel/issues/3576 > [i915#3921]: https://gitlab.freedesktop.org/drm/intel/issues/3921 > [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402 > [i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103 > [i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312 > [i915#4494]: https://gitlab.freedesktop.org/drm/intel/issues/4494 > [i915#4890]: https://gitlab.freedesktop.org/drm/intel/issues/4890 > [i915#4957]: https://gitlab.freedesktop.org/drm/intel/issues/4957 > [i915#5122]: https://gitlab.freedesktop.org/drm/intel/issues/5122 > > > Build changes > ------------- > > * Linux: CI_DRM_11693 -> Patchwork_104244v2 > > CI-20190529: 20190529 > CI_DRM_11693: 14289bc81309b2126f4ba9f339837dacf34ddf9c @ git://anongit.freedesktop.org/gfx-ci/linux > IGT_6485: 51663917b40d36086cc1c555ce4f67b22937694d @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git > Patchwork_104244v2: 14289bc81309b2126f4ba9f339837dacf34ddf9c @ git://anongit.freedesktop.org/gfx-ci/linux > > > ### Linux commits > > e3100146e9db drm/i915/pvc: Add SSEU changes > 920dde2397e4 drm/i915/sseu: Disassociate internal subslice mask representation from uapi > 67224fa58023 drm/i915/sseu: Don't try to store EU mask internally in UAPI format > ec3d320f5b49 drm/i915/sseu: Simplify gen11+ SSEU handling > f00314dcab14 drm/i915/xehp: Drop GETPARAM lookups of I915_PARAM_[SUB]SLICE_MASK > 5edcd0a4da5f drm/i915/xehp: Use separate sseu init function > > == Logs == > > For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/index.html
On 21/05/2022 00:04, Matt Roper wrote: > This series reworks i915's internal handling of slice/subslice/EU (SSEU) > data to represent platforms like Xe_HP in a more natural manner and to > prepare for future platforms where the masks will need to grow in size. > One key idea of this series is that although we have a fixed ABI to > convey SSEU data to userspace (i.e., multiple u8[] arrays with data > stored at different strides), we don't need to use this cumbersome > format for the driver's own internal storage. As long as we can convert > into the uapi form properly when responding to the I915_QUERY ioctl, > it's preferable to use an internal storage format that's easier for the > driver to work with. > > Another key point here is that we're reaching the point where subslice > (DSS) masks will soon not fit within simple u32/u64 integer values. > Xe_HP SDV and DG2 platforms today have subslice (DSS) masks that are 32 > bits, which maxes out the current storage of a u32. With PVC the masks > are represented by a pair of 32-bit registers, requiring a bump up to at > least 64-bits of storage internally. We could switch to u64 for that in > the short term, but since we already know that upcoming architectures > intend to provide DSS fuse bits via three or more registers it's best to > switch to a representation that's more future-proof but still easy to > work with in the driver code. To accomodate this, we start storing our > subslice mask for Xe_HP and beyond in a new typedef that can be > processed by the linux/bitmap.h operations. > > Finally, since no userspace for Xe_HP or beyond is using the legacy > I915_GETPARAM ioctl lookups for I915_PARAM_SLICE_MASK and > I915_PARAM_SUBSLICE_MASK (since they've migrated to the more flexible > I915_QUERY ioctl that can return more than a simple u32 value), we take > the opportunity to officially drop support for those GETPARAM lookups on > modern platforms. Maintaining support for these GETPARAM lookups don't > make sense for a number of reasons: > > * Traditional slices no longer exist, and newer ideas like gslices, > cslices, mslices, etc. aren't something userspace needs to query > since it can be inferred from other information. > * The GETPARAM ioctl doesn't have a way to distinguish between geometry > subslice masks and compute subslice masks, which are distinct on > Xe_HP and beyond. > * The I915_GETPARAM ioctl is limited to returning a 32-bit value, so > when subslice masks begin to exceed 32-bits (on PVC), it simply can't > return the entire mask. > * The GETPARAM ioctl doesn't have a way to give sensible information > for multi-tile devices. > > v2: > - Switch to union of hsw/xehp formats to keep the representation in a > natural format for different types of hardware. > - Avoid accessing internals of intel_sseu_ss_mask_t directly outside of > intel_sseu.[ch]. > - Include PVC SSEU which needs the larger SS mask storage enabled by > this series. > > v3: > - Correct a BIT(s) typo that should have been BIT(ss), causing > incorrect handling on gen9 platforms. > > v4: > - Eliminate sseu->{ss,eu}_stride fields and just calculate the proper > value in the UAPI code that needs them. > - Handle unwanted ~u8 sign extension at the callsite instead of inside > sseu_set_eus. > - Use BITMAP_BITS() macro rather than passing I915_MAX_SS_FUSE_BITS > around directly to bitmap operations. > - Improved debugfs / dmesg reporting for Xe_HP dumps > - Various assertion check improvements. > > Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com> > > > Matt Roper (6): > drm/i915/xehp: Use separate sseu init function > drm/i915/xehp: Drop GETPARAM lookups of I915_PARAM_[SUB]SLICE_MASK > drm/i915/sseu: Simplify gen11+ SSEU handling > drm/i915/sseu: Don't try to store EU mask internally in UAPI format > drm/i915/sseu: Disassociate internal subslice mask representation from > uapi > drm/i915/pvc: Add SSEU changes For the series: Acked-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Almost r-b actually, but I do not feel completely comfortable that I read everything closely enough to not have missed something. So I prefer someone else does a really detailed pass to be sure. Regards, Tvrtko > > drivers/gpu/drm/i915/gem/i915_gem_context.c | 5 +- > drivers/gpu/drm/i915/gt/intel_engine_cs.c | 4 +- > drivers/gpu/drm/i915/gt/intel_gt.c | 12 +- > drivers/gpu/drm/i915/gt/intel_gt_regs.h | 1 + > drivers/gpu/drm/i915/gt/intel_sseu.c | 450 ++++++++++++------- > drivers/gpu/drm/i915/gt/intel_sseu.h | 94 ++-- > drivers/gpu/drm/i915/gt/intel_sseu_debugfs.c | 30 +- > drivers/gpu/drm/i915/gt/intel_workarounds.c | 24 +- > drivers/gpu/drm/i915/i915_drv.h | 2 + > drivers/gpu/drm/i915/i915_getparam.c | 11 +- > drivers/gpu/drm/i915/i915_pci.c | 3 +- > drivers/gpu/drm/i915/i915_query.c | 26 +- > drivers/gpu/drm/i915/intel_device_info.h | 1 + > 13 files changed, 398 insertions(+), 265 deletions(-) >
CI: boot test failure seems to fail always in the same manner. https://gitlab.freedesktop.org/drm/intel/-/issues/6074 BDW: CI:Boot - fail - No warnings/errors I believe the shards failures is unrelated (as there no logs) to this patch. So I created a generic bug for GEN9 to track of failures that doesn't have logs. This bug will be reviewed weekly by the team. https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/shard-skl3/igt@i915_selftest@live@dmabuf.html https://gitlab.freedesktop.org/drm/intel/-/issues/6075 Thanks, Lakshmi. -----Original Message----- From: Roper, Matthew D <matthew.d.roper@intel.com> Sent: Monday, May 23, 2022 4:32 PM To: intel-gfx@lists.freedesktop.org Cc: Vudum, Lakshminarayana <lakshminarayana.vudum@intel.com> Subject: Re: ✗ Fi.CI.BAT: failure for i915: SSEU handling updates (rev2) On Mon, May 23, 2022 at 09:23:33PM +0000, Patchwork wrote: > == Series Details == > > Series: i915: SSEU handling updates (rev2) > URL : https://patchwork.freedesktop.org/series/104244/ > State : failure > > == Summary == > > CI Bug Log - changes from CI_DRM_11693 -> Patchwork_104244v2 > ==================================================== > > Summary > ------- > > **FAILURE** > > Serious unknown changes coming with Patchwork_104244v2 absolutely need to be > verified manually. > > If you think the reported changes have nothing to do with the changes > introduced in Patchwork_104244v2, please notify your bug team to allow them > to document this new failure mode, which will reduce false positives in CI. > > External URL: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/index.html > > Participating hosts (44 -> 45) > ------------------------------ > > Additional (2): fi-icl-u2 fi-tgl-u2 > Missing (1): fi-hsw-4770 > > Possible new issues > ------------------- > > Here are the unknown changes that may have been introduced in Patchwork_104244v2: > > ### CI changes ### > > #### Possible regressions #### > > * boot: > - fi-bdw-5557u: [PASS][1] -> [FAIL][2] > [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11693/fi-bdw-5557u/boot.html > [2]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/fi-bdw-555 > 7u/boot.html I don't see a boot failure here? It looks like i915 loaded successfully, without errors. It also looks like more tests ran successfully on the machine after that as well. Matt > > > Known issues > ------------ > > Here are the changes found in Patchwork_104244v2 that come from known issues: > > ### IGT changes ### > > #### Issues hit #### > > * igt@gem_exec_gttfill@basic: > - fi-icl-u2: NOTRUN -> [INCOMPLETE][3] ([i915#4890]) > [3]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/fi-icl-u2/ > igt@gem_exec_gttfill@basic.html > > * igt@gem_huc_copy@huc-copy: > - fi-tgl-u2: NOTRUN -> [SKIP][4] ([i915#2190]) > [4]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/fi-tgl-u2/ > igt@gem_huc_copy@huc-copy.html > > * igt@i915_selftest@live@hangcheck: > - bat-dg1-6: [PASS][5] -> [DMESG-FAIL][6] ([i915#4494] / [i915#4957]) > [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11693/bat-dg1-6/igt@i915_selftest@live@hangcheck.html > [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/bat-dg1-6/igt@i915_selftest@live@hangcheck.html > - fi-snb-2600: [PASS][7] -> [INCOMPLETE][8] ([i915#3921]) > [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11693/fi-snb-2600/igt@i915_selftest@live@hangcheck.html > [8]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/fi-snb-260 > 0/igt@i915_selftest@live@hangcheck.html > > * igt@kms_busy@basic@flip: > - fi-tgl-u2: NOTRUN -> [DMESG-WARN][9] ([i915#402]) +3 similar issues > [9]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/fi-tgl-u2/ > igt@kms_busy@basic@flip.html > > * igt@kms_chamelium@dp-hpd-fast: > - fi-tgl-u2: NOTRUN -> [SKIP][10] ([fdo#109284] / [fdo#111827]) +7 similar issues > [10]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/fi-tgl-u2/ > igt@kms_chamelium@dp-hpd-fast.html > > * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic: > - fi-tgl-u2: NOTRUN -> [SKIP][11] ([i915#4103]) +1 similar issue > [11]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/fi-tgl-u2/ > igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html > > * igt@kms_flip@basic-flip-vs-modeset@b-edp1: > - bat-adlp-4: [PASS][12] -> [DMESG-WARN][13] ([i915#3576]) > [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11693/bat-adlp-4/igt@kms_flip@basic-flip-vs-modeset@b-edp1.html > [13]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/bat-adlp-4 > /igt@kms_flip@basic-flip-vs-modeset@b-edp1.html > > * igt@kms_force_connector_basic@force-load-detect: > - fi-tgl-u2: NOTRUN -> [SKIP][14] ([fdo#109285]) > [14]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/fi-tgl-u2/ > igt@kms_force_connector_basic@force-load-detect.html > > * igt@kms_setmode@basic-clone-single-crtc: > - fi-tgl-u2: NOTRUN -> [SKIP][15] ([i915#3555]) > [15]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/fi-tgl-u2/ > igt@kms_setmode@basic-clone-single-crtc.html > > * igt@prime_vgem@basic-userptr: > - fi-tgl-u2: NOTRUN -> [SKIP][16] ([i915#3301]) > [16]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/fi-tgl-u2/ > igt@prime_vgem@basic-userptr.html > > * igt@runner@aborted: > - fi-icl-u2: NOTRUN -> [FAIL][17] ([i915#4312]) > [17]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/fi-icl-u2/ > igt@runner@aborted.html > > > #### Possible fixes #### > > * igt@gem_exec_suspend@basic-s0@smem: > - {fi-ehl-2}: [DMESG-WARN][18] ([i915#5122]) -> [PASS][19] > [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11693/fi-ehl-2/igt@gem_exec_suspend@basic-s0@smem.html > [19]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/fi-ehl-2/i > gt@gem_exec_suspend@basic-s0@smem.html > > * igt@kms_flip@basic-plain-flip@a-edp1: > - bat-adlp-4: [DMESG-WARN][20] ([i915#3576]) -> [PASS][21] +2 similar issues > [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11693/bat-adlp-4/igt@kms_flip@basic-plain-flip@a-edp1.html > [21]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/bat-adlp-4 > /igt@kms_flip@basic-plain-flip@a-edp1.html > > > {name}: This element is suppressed. This means it is ignored when computing > the status of the difference (SUCCESS, WARNING, or FAILURE). > > [fdo#109284]: https://bugs.freedesktop.org/show_bug.cgi?id=109284 > [fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285 > [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827 > [i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190 > [i915#3301]: https://gitlab.freedesktop.org/drm/intel/issues/3301 > [i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555 > [i915#3576]: https://gitlab.freedesktop.org/drm/intel/issues/3576 > [i915#3921]: https://gitlab.freedesktop.org/drm/intel/issues/3921 > [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402 > [i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103 > [i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312 > [i915#4494]: https://gitlab.freedesktop.org/drm/intel/issues/4494 > [i915#4890]: https://gitlab.freedesktop.org/drm/intel/issues/4890 > [i915#4957]: https://gitlab.freedesktop.org/drm/intel/issues/4957 > [i915#5122]: https://gitlab.freedesktop.org/drm/intel/issues/5122 > > > Build changes > ------------- > > * Linux: CI_DRM_11693 -> Patchwork_104244v2 > > CI-20190529: 20190529 > CI_DRM_11693: 14289bc81309b2126f4ba9f339837dacf34ddf9c @ git://anongit.freedesktop.org/gfx-ci/linux > IGT_6485: 51663917b40d36086cc1c555ce4f67b22937694d @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git > Patchwork_104244v2: 14289bc81309b2126f4ba9f339837dacf34ddf9c @ > git://anongit.freedesktop.org/gfx-ci/linux > > > ### Linux commits > > e3100146e9db drm/i915/pvc: Add SSEU changes > 920dde2397e4 drm/i915/sseu: Disassociate internal subslice mask > representation from uapi > 67224fa58023 drm/i915/sseu: Don't try to store EU mask internally in > UAPI format > ec3d320f5b49 drm/i915/sseu: Simplify gen11+ SSEU handling > f00314dcab14 drm/i915/xehp: Drop GETPARAM lookups of > I915_PARAM_[SUB]SLICE_MASK 5edcd0a4da5f drm/i915/xehp: Use separate > sseu init function > > == Logs == > > For more details see: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/index.html -- Matt Roper Graphics Software Engineer VTT-OSGC Platform Enablement Intel Corporation
This series reworks i915's internal handling of slice/subslice/EU (SSEU) data to represent platforms like Xe_HP in a more natural manner and to prepare for future platforms where the masks will need to grow in size. One key idea of this series is that although we have a fixed ABI to convey SSEU data to userspace (i.e., multiple u8[] arrays with data stored at different strides), we don't need to use this cumbersome format for the driver's own internal storage. As long as we can convert into the uapi form properly when responding to the I915_QUERY ioctl, it's preferable to use an internal storage format that's easier for the driver to work with. Another key point here is that we're reaching the point where subslice (DSS) masks will soon not fit within simple u32/u64 integer values. Xe_HP SDV and DG2 platforms today have subslice (DSS) masks that are 32 bits, which maxes out the current storage of a u32. With PVC the masks are represented by a pair of 32-bit registers, requiring a bump up to at least 64-bits of storage internally. We could switch to u64 for that in the short term, but since we already know that upcoming architectures intend to provide DSS fuse bits via three or more registers it's best to switch to a representation that's more future-proof but still easy to work with in the driver code. To accomodate this, we start storing our subslice mask for Xe_HP and beyond in a new typedef that can be processed by the linux/bitmap.h operations. Finally, since no userspace for Xe_HP or beyond is using the legacy I915_GETPARAM ioctl lookups for I915_PARAM_SLICE_MASK and I915_PARAM_SUBSLICE_MASK (since they've migrated to the more flexible I915_QUERY ioctl that can return more than a simple u32 value), we take the opportunity to officially drop support for those GETPARAM lookups on modern platforms. Maintaining support for these GETPARAM lookups don't make sense for a number of reasons: * Traditional slices no longer exist, and newer ideas like gslices, cslices, mslices, etc. aren't something userspace needs to query since it can be inferred from other information. * The GETPARAM ioctl doesn't have a way to distinguish between geometry subslice masks and compute subslice masks, which are distinct on Xe_HP and beyond. * The I915_GETPARAM ioctl is limited to returning a 32-bit value, so when subslice masks begin to exceed 32-bits (on PVC), it simply can't return the entire mask. * The GETPARAM ioctl doesn't have a way to give sensible information for multi-tile devices. v2: - Switch to union of hsw/xehp formats to keep the representation in a natural format for different types of hardware. - Avoid accessing internals of intel_sseu_ss_mask_t directly outside of intel_sseu.[ch]. - Include PVC SSEU which needs the larger SS mask storage enabled by this series. v3: - Correct a BIT(s) typo that should have been BIT(ss), causing incorrect handling on gen9 platforms. v4: - Eliminate sseu->{ss,eu}_stride fields and just calculate the proper value in the UAPI code that needs them. - Handle unwanted ~u8 sign extension at the callsite instead of inside sseu_set_eus. - Use BITMAP_BITS() macro rather than passing I915_MAX_SS_FUSE_BITS around directly to bitmap operations. - Improved debugfs / dmesg reporting for Xe_HP dumps - Various assertion check improvements. Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com> Matt Roper (6): drm/i915/xehp: Use separate sseu init function drm/i915/xehp: Drop GETPARAM lookups of I915_PARAM_[SUB]SLICE_MASK drm/i915/sseu: Simplify gen11+ SSEU handling drm/i915/sseu: Don't try to store EU mask internally in UAPI format drm/i915/sseu: Disassociate internal subslice mask representation from uapi drm/i915/pvc: Add SSEU changes drivers/gpu/drm/i915/gem/i915_gem_context.c | 5 +- drivers/gpu/drm/i915/gt/intel_engine_cs.c | 4 +- drivers/gpu/drm/i915/gt/intel_gt.c | 12 +- drivers/gpu/drm/i915/gt/intel_gt_regs.h | 1 + drivers/gpu/drm/i915/gt/intel_sseu.c | 450 ++++++++++++------- drivers/gpu/drm/i915/gt/intel_sseu.h | 94 ++-- drivers/gpu/drm/i915/gt/intel_sseu_debugfs.c | 30 +- drivers/gpu/drm/i915/gt/intel_workarounds.c | 24 +- drivers/gpu/drm/i915/i915_drv.h | 2 + drivers/gpu/drm/i915/i915_getparam.c | 11 +- drivers/gpu/drm/i915/i915_pci.c | 3 +- drivers/gpu/drm/i915/i915_query.c | 26 +- drivers/gpu/drm/i915/intel_device_info.h | 1 + 13 files changed, 398 insertions(+), 265 deletions(-)