mbox series

[v3,0/2] Correction to QGV related register addresses

Message ID 20230323114426.41136-1-vinod.govindapillai@intel.com (mailing list archive)
Headers show
Series Correction to QGV related register addresses | expand

Message

Govindapillai, Vinod March 23, 2023, 11:44 a.m. UTC 
Wrong offsets are calculated to read QGV points from mem ss. Also
a wrong register address is used to get the sagv block time. Fix
these two issues.

Vinod Govindapillai (2):
  drm/i915/reg: fix QGV points register access offsets
  drm/i915/reg: use the correct register to access SAGV block time

 drivers/gpu/drm/i915/i915_reg.h | 7 ++++---
 1 file changed, 4 insertions(+), 3 deletions(-)