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[0/1] HDMI 2.0/DP1p62Gbps skew violation when there is skew between DL PCLK

Message ID 20230627153451.2834196-1-mitulkumar.ajitkumar.golani@intel.com (mailing list archive)
Headers show
Series HDMI 2.0/DP1p62Gbps skew violation when there is skew between DL PCLK | expand

Message

Golani, Mitulkumar Ajitkumar June 27, 2023, 3:34 p.m. UTC 
When doing type-C PHY voltage swing programming for HDMI and DP 1.62Gbps,
program DKLP_PCS_GLUE_TX_DPCNTL2[loadgen_sharing_pmd_disable] to '1'.
For other DP frequencies, program DKLP_PCS_GLUE_TX_DPCNTL2[loadgen_sharing_pmd_disable]
to '0'.

This Workaround is specific to Display Version 13
Wa_15010727533

Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>

Mitul Golani (1):
  drm/i915/display: HDMI2.0/DP1p62Gbps skew violation when there is skew
    between DL PCLK

 drivers/gpu/drm/i915/display/intel_ddi.c | 13 +++++++++++++
 drivers/gpu/drm/i915/i915_reg.h          |  6 ++++++
 2 files changed, 19 insertions(+)