From patchwork Tue Oct 10 15:02:37 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Cavitt, Jonathan" X-Patchwork-Id: 13415699 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 4433DCD8CA4 for ; Tue, 10 Oct 2023 15:13:29 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id B3D1710E32C; Tue, 10 Oct 2023 15:13:28 +0000 (UTC) Received: from mgamail.intel.com (mgamail.intel.com [192.55.52.88]) by gabe.freedesktop.org (Postfix) with ESMTPS id A24FB10E32C for ; Tue, 10 Oct 2023 15:13:27 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1696950807; x=1728486807; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=DJSijsZ3lQcx/jNKJB0XodXea7HtnRLaMrQaZELi/Nk=; b=NqsCGYmbdzVR6Fcib99THHQq61nQxJzrsYt6fF9c1kL8miSgUau2NFXC GcDmiljxw3SNaLTzF7yBNl+fj/Joq8JuR0hlIXz5Wzs9JFCm2Xn4cCtaG HAQA+hp9CFtheXWd/Uou/i5KhK5thos2qlA12squ64u9HcRVb9cmYTIZm B5maZhWHz1BvhPWgcs0F9S68QVulRJgmHZW3iWnPe098duSXUD4VHxaCW t0dVA3AAYT39JM3uOGr806TLRk1h/+XCa0jDqmNtkXNjiFgezBguyDDhm 5zgqPtNBMLkQJpM13zom0Pcw6QliKpAHow2jtSWlBEVPxeF0uL8+MB0Wx g==; X-IronPort-AV: E=McAfee;i="6600,9927,10859"; a="415435731" X-IronPort-AV: E=Sophos;i="6.03,213,1694761200"; d="scan'208";a="415435731" Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 Oct 2023 08:13:27 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10859"; a="757154978" X-IronPort-AV: E=Sophos;i="6.03,213,1694761200"; d="scan'208";a="757154978" Received: from dut-internal-9dd7.jf.intel.com ([10.165.21.194]) by fmsmga007-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 Oct 2023 08:13:26 -0700 From: Jonathan Cavitt To: intel-gfx@lists.freedesktop.org Date: Tue, 10 Oct 2023 08:02:37 -0700 Message-Id: <20231010150244.2021420-1-jonathan.cavitt@intel.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH v10 0/7] drm/i915: Define and use GuC and CTB TLB invalidation routines X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: janusz.krzysztofik@intel.com, andi.shyti@intel.com, matthew.d.roper@intel.com, jonathan.cavitt@intel.com, saurabhg.gupta@intel.com, chris.p.wilson@linux.intel.com, nirmoy.das@intel.com Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Implement GuC-based TLB invalidations and use them on MTL. v2: - Add missing supporting patches. v3: - Split suspend/resume changes and multi-gt support into separate patches. - Only perform GuC TLB invalidation functions when supported. - Move intel_guc_is_enabled check function to usage location. - Address comments. v4: - Change conditions for GuC-based tlb invalidation support to a pci tag that's only active for MTL. - Address some FIXMEs and formatting issues. - Move suspend/resume changes to helper functions in intel_gt.h - Improve comment for ct_handle_event change. - Use cleaner if-else conditions. - Address comments. v5: - Reintroduce missing change to selftest msleep duration - Move suspend/resume loops from intel_gt.h to intel_tlb.c, making them no longer static inlines. - Remove superfluous blocking and error checks. - Move ct_handle_event exception to general case in ct_process_request. - Explain usage of xa_alloc_cyclic_irq. - Modify explanation of purpose of OUTSTANDING_GUC_TIMEOUT_PERIOD macro. - Explain purpose of performing tlb invalidation twice in intel_gt_tlb_resume_all. v6: - Add this cover letter. - Fix explanation of purpose of OUTSTANDING_GUC_TIMEOUT_PERIOD macro again. - s/pci tags/pci flags - Enable GuC TLB Invalidations separately from adding the flags to do so. v7: - Eliminate pci terminology from patches. - Order new device info flag correctly. - Run gen8_ggtt_invalidate in more cases, specifically when GuC-based TLB invalidation is not supported. - Use intel_uncore_write_fw instead of intel_uncore_write during guc_ggtt_invalidate. - Remove duplicate request message clear in ct_process_request. - Remove faulty tag from series. v8: - Simplify cover letter contents. - Fix miscellaneous formatting and typos. - Reorder device info flags and defines. - Reword commit message. - Rename TLB invalidation enums and functions. - Add comments explaining confusing points. - Add helper function getting expected delay of CT buffer. - Simplify intel_guc_tlb_invalidation_done by passing computed values. - Remove helper functions for tlb suspend and resume. - Move tlb suspend and resume paths to uc. - Split suspend/resume and wedged into two patches. - Clarify purpose of sleep change in tlb selftest. v9: - Explain complexity of GuC TLB invalidations as required for range-based TLB invalidations, which will be platformed later. - Fix CHECKPATCH issues. - Explain intel_guc_is_ready tlb invalidation skip in intel_gt_invalidate_tlb_full. - Reword comment for unlocked xa_for_each loop in intel_guc_submission_reset. - Report all errors in init_tlb_lookup. - Remove debug message from fini_tlb_lookup. - Use standardized interface for intel_guc_tlb_invalidation_done - Remove spurious changes. - Move wake_up_all_tlb_invalidate on wedge to correct patch. v10: - Add lock to tlb_lookup on guc submission reset. - Add comment about why timeout increased from 10 ms to 20 ms by default in gt_tlb selftest. - Remove spurious changes. Jonathan Cavitt (6): drm/i915: Add GuC TLB Invalidation device info flags drm/i915/guc: Add CT size delay helper drm/i915: No TLB invalidation on suspended GT drm/i915: No TLB invalidation on wedged GT drm/i915/gt: Increase sleep in gt_tlb selftest sanitycheck drm/i915: Enable GuC TLB invalidations for MTL Prathap Kumar Valsan (1): drm/i915: Define and use GuC and CTB TLB invalidation routines drivers/gpu/drm/i915/gt/intel_ggtt.c | 34 ++- drivers/gpu/drm/i915/gt/intel_tlb.c | 16 +- drivers/gpu/drm/i915/gt/selftest_tlb.c | 11 +- .../gpu/drm/i915/gt/uc/abi/guc_actions_abi.h | 33 +++ drivers/gpu/drm/i915/gt/uc/intel_guc.h | 23 ++ drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c | 4 + drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h | 13 ++ drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h | 1 + .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 211 +++++++++++++++++- drivers/gpu/drm/i915/gt/uc/intel_uc.c | 7 + drivers/gpu/drm/i915/i915_drv.h | 2 + drivers/gpu/drm/i915/i915_pci.c | 1 + drivers/gpu/drm/i915/intel_device_info.h | 1 + 13 files changed, 343 insertions(+), 14 deletions(-) Reviewed-by: Andi Shyti