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[0/8] drm/i915: cdclk/voltage_level cleanups and fixes

Message ID 20231128115138.13238-1-ville.syrjala@linux.intel.com (mailing list archive)
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Series drm/i915: cdclk/voltage_level cleanups and fixes | expand

Message

Ville Syrjälä Nov. 28, 2023, 11:51 a.m. UTC 
From: Ville Syrjälä <ville.syrjala@linux.intel.com>

A bit of refactoring around the cdclk/voltage_level stuff.

I also spotted that we were miscalculating the voltage level
on MTL in two different places, so included fixes (or rather
power optimizations) for those.

Ville Syrjälä (8):
  drm/i915/cdclk: s/-1/~0/ when dealing with unsigned values
  drm/i915/cdclk: Give the squash waveform length a name
  drm/i915/cdclk: Remove the assumption that cd2x div==2 when using
    squashing
  drm/i915/cdclk: Rewrite cdclk->voltage_level selection to use tables
  drm/i915/mtl: Fix voltage_level for cdclk==480MHz
  drm/i915: Split intel_ddi_compute_min_voltage_level() into platform
    variants
  drm/i915/mtl: Calculate the correct voltage level from port_clock
  drm/i915: Simplify intel_ddi_compute_min_voltage_level()

 drivers/gpu/drm/i915/display/intel_cdclk.c  | 101 ++++++++++++--------
 drivers/gpu/drm/i915/display/intel_ddi.c    |  50 +++++++---
 drivers/gpu/drm/i915/display/intel_ddi.h    |   3 +-
 drivers/gpu/drm/i915/display/intel_dp_mst.c |   2 +-
 4 files changed, 102 insertions(+), 54 deletions(-)