mbox series

[0/7] HDCP Type1 MST fixes

Message ID 20240112074120.159797-1-suraj.kandpal@intel.com (mailing list archive)
Headers show
Series HDCP Type1 MST fixes | expand

Message

Kandpal, Suraj Jan. 12, 2024, 7:41 a.m. UTC 
We were seeing a blank screen whenever Type1 content was played.
This was due to extra timing which was taken as we had moved to
remote read and writes previously for MST scenario, which in turn
was done as we were not able to do direct read and writes to the
immediate downstream device.
The correct flow should be that we talk only to the immediate
downstream device and the rest needs to be taken care by that device.
With this patch series we move back to direct reads and writes,
fix the fastset setting because of which direct reads and writes to
HDCP related DPCD register stopped working, derive hdcp structure
correctly and increase robustability if rxcaps HDCP capability
reporting.

Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>

Suraj Kandpal (6):
  drm/i915/hdcp: Move to direct reads for HDCP
  drm/i915/hdcp: HDCP Capability for the downstream device
  drm/i915/hdcp: Remove additional timing for reading mst hdcp message
  drm/i915/hdcp: Extract hdcp structure from correct connector
  drm/i915/hdcp: Allocate stream id after HDCP AKE stage
  drm/i915/hdcp: Read Rxcaps for robustibility

Ville Syrjälä (1):
  drm/i915/display: fastset tbt pll thing

 .../drm/i915/display/intel_display_debugfs.c  |  19 ++-
 .../drm/i915/display/intel_display_types.h    |   3 +-
 drivers/gpu/drm/i915/display/intel_dp_hdcp.c  |  54 ++++----
 drivers/gpu/drm/i915/display/intel_dpll_mgr.c |   8 +-
 drivers/gpu/drm/i915/display/intel_hdcp.c     | 130 ++++++++----------
 drivers/gpu/drm/i915/display/intel_hdcp.h     |   2 +-
 drivers/gpu/drm/i915/display/intel_hdmi.c     |   2 +-
 7 files changed, 115 insertions(+), 103 deletions(-)