| Message ID | 20240213064835.139464-1-uma.shankar@intel.com (mailing list archive) |
|---|---|
| Headers | show |
| Series | Plane Color Pipeline support for Intel platforms | expand |
On Tue, 13 Feb 2024 12:18:07 +0530 Uma Shankar <uma.shankar@intel.com> wrote: > This series intends to add support for Plane Color Management for > Intel platforms. This is based on the design which has been agreed > upon by the community. Series implementing the design for generic > DRM core has been sent out by Harry Wentland and is under review > below: > https://patchwork.freedesktop.org/series/123446/ > > The base work of above series is squashed under 1 patch and support > for Intel platform is added on top of it. > Any reviews on the original core design is expected to be done in > Harry's series to avoid any forking of the discussion. > > We have added some changes/fixes to the Harry's core DRM changes, > being put up as separate patches on top of squashed patch. These are > expected to get included in the main series from Harry once agreed upon. > > Changes added on core design: > 1. Below patches implement some fixes on original series > drm: Add missing function declarations > drm: handle NULL next colorop in drm_colorop_set_next_property > drm: Fix error logging in set Color Pipeline > > 2. Implemented a HW capability property to expose segmented luts. > drm: Add Color lut range attributes > drm: Add Color ops capability property > drm: Define helper to create color ops capability property > drm: Define helper for adding capability property for 1D LUT > > This helps in generically defining the hardware lut capabilities, > lut distribution, precision, segmented or PWL LUTS. > > 3. Added support for enhanced prescision, 3x3 matrix and 1d LUT: > drm: Add Enhanced LUT precision structure > drm: Add support for 3x3 CTM > drm: Add 1D LUT color op > > On top of this base work for DRM core plane color pipeline design, > implementation is done for Intel hardware platforms. Below patches > include the same: > > drm/i915: Add identifiers for intel color blocks > drm/i915: Add intel_color_op > drm/i915/color: Add helper to allocate intel colorop > drm/i915/color: Add helper to create intel colorop > drm/i915/color: Create a transfer function color pipeline > drm/i915/color: Add and attach COLORPIPELINE plane property > drm/i915/color: Add framework to set colorop > drm/i915/color: Add callbacks to set plane CTM > drm/i915/color: Add framework to program PRE/POST CSC LUT > FIXME: force disable legacy plane color properties for TGL and beyond > drm/i915/color: Enable Plane Color Pipelines > drm/i915: Define segmented Lut and add capabilities to colorop > drm/i915/color: Add plane CTM callback for TGL and beyond > drm/i915: Add register definitions for Plane Degamma > drm/i915: Add register definitions for Plane Post CSC > drm/i915/color: Program Pre-CSC registers > drm/i915/xelpd: Program Plane Post CSC Registers > > Bhanu from Intel will be sending out the igt changes to help test the > color pipeline implementation based on the current igt changes sent out > by Harry. > https://patchwork.freedesktop.org/series/123448/ > > Planned Next Steps: > 1. Work with Harry and community and get DRM core changes for color > pipeline merged. > 2. Implement pipe color management (post blending) based on the current > color pipeline design. > 3. Work with compositor maintainers to get color processing implemented > using display hardware, thereby avoid any GL or GPU shaders. > > Thanks to all the community maintainers and contributors who have helped > to get this support in upstream Linux. Looking forward to collaborate, > work together and get this merged. > ... > Chaitanya Kumar Borah (16): > drm: Add missing function declarations > drm: handle NULL next colorop in drm_colorop_set_next_property > drm: Fix error logging in set Color Pipeline > drm: Add support for 3x3 CTM > drm: Add 1D LUT color op > drm/i915: Add identifiers for intel color blocks > drm/i915: Add intel_color_op > drm/i915/color: Add helper to allocate intel colorop > drm/i915/color: Add helper to create intel colorop > drm/i915/color: Create a transfer function color pipeline > drm/i915/color: Add and attach COLORPIPELINE plane property > drm/i915/color: Add framework to set colorop > drm/i915/color: Add callbacks to set plane CTM > drm/i915/color: Add framework to program PRE/POST CSC LUT > FIXME: force disable legacy plane color properties for TGL and beyond > drm/i915/color: Enable Plane Color Pipelines > > Harry Wentland (1): > [NOT FOR REVIEW] drm: color pipeline base work > > Uma Shankar (11): > drm: Add Enhanced LUT precision structure > drm: Add Color lut range attributes > drm: Add Color ops capability property > drm: Define helper to create color ops capability property > drm: Define helper for adding capability property for 1D LUT > drm/i915: Define segmented Lut and add capabilities to colorop > drm/i915/color: Add plane CTM callback for TGL and beyond > drm/i915: Add register definitions for Plane Degamma > drm/i915: Add register definitions for Plane Post CSC > drm/i915/color: Program Pre-CSC registers > drm/i915/xelpd: Program Plane Post CSC Registers Hi Uma, it is really hard for me to get a good picture of what this would result in from userspace perspective, which properties will exist with what values, but I didn't spot any fundamental UAPI design problems so far. Thanks, pq
> -----Original Message----- > From: Pekka Paalanen <pekka.paalanen@haloniitty.fi> > Sent: Tuesday, February 13, 2024 4:32 PM > To: Shankar, Uma <uma.shankar@intel.com> > Cc: intel-gfx@lists.freedesktop.org; dri-devel@lists.freedesktop.org; > ville.syrjala@linux.intel.com; contact@emersion.fr; harry.wentland@amd.com; > mwen@igalia.com; jadahl@redhat.com; sebastian.wick@redhat.com; > shashank.sharma@amd.com; agoins@nvidia.com; joshua@froggi.es; > mdaenzer@redhat.com; aleixpol@kde.org; xaver.hugl@gmail.com; > victoria@system76.com; daniel@ffwll.ch; quic_naseer@quicinc.com; > quic_cbraga@quicinc.com; quic_abhinavk@quicinc.com; arthurgrillo@riseup.net; > marcan@marcan.st; Liviu.Dudau@arm.com; sashamcintosh@google.com; > sean@poorly.run; Borah, Chaitanya Kumar <chaitanya.kumar.borah@intel.com> > Subject: Re: [PATCH 00/28] Plane Color Pipeline support for Intel platforms > > On Tue, 13 Feb 2024 12:18:07 +0530 > Uma Shankar <uma.shankar@intel.com> wrote: > > > This series intends to add support for Plane Color Management for > > Intel platforms. This is based on the design which has been agreed > > upon by the community. Series implementing the design for generic DRM > > core has been sent out by Harry Wentland and is under review > > below: > > https://patchwork.freedesktop.org/series/123446/ > > > > The base work of above series is squashed under 1 patch and support > > for Intel platform is added on top of it. > > Any reviews on the original core design is expected to be done in > > Harry's series to avoid any forking of the discussion. > > > > We have added some changes/fixes to the Harry's core DRM changes, > > being put up as separate patches on top of squashed patch. These are > > expected to get included in the main series from Harry once agreed upon. > > > > Changes added on core design: > > 1. Below patches implement some fixes on original series > > drm: Add missing function declarations > > drm: handle NULL next colorop in drm_colorop_set_next_property > > drm: Fix error logging in set Color Pipeline > > > > 2. Implemented a HW capability property to expose segmented luts. > > drm: Add Color lut range attributes > > drm: Add Color ops capability property > > drm: Define helper to create color ops capability property > > drm: Define helper for adding capability property for 1D LUT > > > > This helps in generically defining the hardware lut capabilities, lut > > distribution, precision, segmented or PWL LUTS. > > > > 3. Added support for enhanced prescision, 3x3 matrix and 1d LUT: > > drm: Add Enhanced LUT precision structure > > drm: Add support for 3x3 CTM > > drm: Add 1D LUT color op > > > > On top of this base work for DRM core plane color pipeline design, > > implementation is done for Intel hardware platforms. Below patches > > include the same: > > > > drm/i915: Add identifiers for intel color blocks > > drm/i915: Add intel_color_op > > drm/i915/color: Add helper to allocate intel colorop > > drm/i915/color: Add helper to create intel colorop > > drm/i915/color: Create a transfer function color pipeline > > drm/i915/color: Add and attach COLORPIPELINE plane property > > drm/i915/color: Add framework to set colorop > > drm/i915/color: Add callbacks to set plane CTM > > drm/i915/color: Add framework to program PRE/POST CSC LUT > > FIXME: force disable legacy plane color properties for TGL and beyond > > drm/i915/color: Enable Plane Color Pipelines > > drm/i915: Define segmented Lut and add capabilities to colorop > > drm/i915/color: Add plane CTM callback for TGL and beyond > > drm/i915: Add register definitions for Plane Degamma > > drm/i915: Add register definitions for Plane Post CSC > > drm/i915/color: Program Pre-CSC registers > > drm/i915/xelpd: Program Plane Post CSC Registers > > > > Bhanu from Intel will be sending out the igt changes to help test the > > color pipeline implementation based on the current igt changes sent > > out by Harry. > > https://patchwork.freedesktop.org/series/123448/ > > > > Planned Next Steps: > > 1. Work with Harry and community and get DRM core changes for color > > pipeline merged. > > 2. Implement pipe color management (post blending) based on the > > current color pipeline design. > > 3. Work with compositor maintainers to get color processing > > implemented using display hardware, thereby avoid any GL or GPU shaders. > > > > Thanks to all the community maintainers and contributors who have > > helped to get this support in upstream Linux. Looking forward to > > collaborate, work together and get this merged. > > > > ... > > > Chaitanya Kumar Borah (16): > > drm: Add missing function declarations > > drm: handle NULL next colorop in drm_colorop_set_next_property > > drm: Fix error logging in set Color Pipeline > > drm: Add support for 3x3 CTM > > drm: Add 1D LUT color op > > drm/i915: Add identifiers for intel color blocks > > drm/i915: Add intel_color_op > > drm/i915/color: Add helper to allocate intel colorop > > drm/i915/color: Add helper to create intel colorop > > drm/i915/color: Create a transfer function color pipeline > > drm/i915/color: Add and attach COLORPIPELINE plane property > > drm/i915/color: Add framework to set colorop > > drm/i915/color: Add callbacks to set plane CTM > > drm/i915/color: Add framework to program PRE/POST CSC LUT > > FIXME: force disable legacy plane color properties for TGL and beyond > > drm/i915/color: Enable Plane Color Pipelines > > > > Harry Wentland (1): > > [NOT FOR REVIEW] drm: color pipeline base work > > > > Uma Shankar (11): > > drm: Add Enhanced LUT precision structure > > drm: Add Color lut range attributes > > drm: Add Color ops capability property > > drm: Define helper to create color ops capability property > > drm: Define helper for adding capability property for 1D LUT > > drm/i915: Define segmented Lut and add capabilities to colorop > > drm/i915/color: Add plane CTM callback for TGL and beyond > > drm/i915: Add register definitions for Plane Degamma > > drm/i915: Add register definitions for Plane Post CSC > > drm/i915/color: Program Pre-CSC registers > > drm/i915/xelpd: Program Plane Post CSC Registers > > > Hi Uma, > > it is really hard for me to get a good picture of what this would result in from > userspace perspective, which properties will exist with what values, but I didn't > spot any fundamental UAPI design problems so far. Hi Pekka, Original idea remains same from Harry's series, we just added 1 more property for advertising hw caps and added 2 additional color op types. Will update the documentation as well to make this clear and readable. We missed to add in this version. Thanks for looking into the series and your valuable inputs. Regards, Uma Shankar > > Thanks, > pq
On 2024-02-13 01:48, Uma Shankar wrote: > This series intends to add support for Plane Color Management for > Intel platforms. This is based on the design which has been agreed > upon by the community. Series implementing the design for generic > DRM core has been sent out by Harry Wentland and is under review > below: > https://patchwork.freedesktop.org/series/123446/ > > The base work of above series is squashed under 1 patch and support > for Intel platform is added on top of it. > Any reviews on the original core design is expected to be done in > Harry's series to avoid any forking of the discussion. > > We have added some changes/fixes to the Harry's core DRM changes, > being put up as separate patches on top of squashed patch. These are > expected to get included in the main series from Harry once agreed upon. > > Changes added on core design: > 1. Below patches implement some fixes on original series > drm: Add missing function declarations > drm: handle NULL next colorop in drm_colorop_set_next_property > drm: Fix error logging in set Color Pipeline > > 2. Implemented a HW capability property to expose segmented luts. > drm: Add Color lut range attributes > drm: Add Color ops capability property > drm: Define helper to create color ops capability property > drm: Define helper for adding capability property for 1D LUT > > This helps in generically defining the hardware lut capabilities, > lut distribution, precision, segmented or PWL LUTS. > > 3. Added support for enhanced prescision, 3x3 matrix and 1d LUT: > drm: Add Enhanced LUT precision structure > drm: Add support for 3x3 CTM > drm: Add 1D LUT color op > > On top of this base work for DRM core plane color pipeline design, > implementation is done for Intel hardware platforms. Below patches > include the same: > > drm/i915: Add identifiers for intel color blocks > drm/i915: Add intel_color_op > drm/i915/color: Add helper to allocate intel colorop > drm/i915/color: Add helper to create intel colorop > drm/i915/color: Create a transfer function color pipeline > drm/i915/color: Add and attach COLORPIPELINE plane property > drm/i915/color: Add framework to set colorop > drm/i915/color: Add callbacks to set plane CTM > drm/i915/color: Add framework to program PRE/POST CSC LUT > FIXME: force disable legacy plane color properties for TGL and beyond > drm/i915/color: Enable Plane Color Pipelines > drm/i915: Define segmented Lut and add capabilities to colorop > drm/i915/color: Add plane CTM callback for TGL and beyond > drm/i915: Add register definitions for Plane Degamma > drm/i915: Add register definitions for Plane Post CSC > drm/i915/color: Program Pre-CSC registers > drm/i915/xelpd: Program Plane Post CSC Registers > > Bhanu from Intel will be sending out the igt changes to help test the > color pipeline implementation based on the current igt changes sent out > by Harry. > https://patchwork.freedesktop.org/series/123448/ > > Planned Next Steps: > 1. Work with Harry and community and get DRM core changes for color > pipeline merged. We'll need a userspace to implement support before merging, but we're working to enabling all color properties gamescope currently uses for the SteamDeck color management to the Color Pipeline API, which should help us get there. It's still a journey but I think the path is clear. I'll send a new version of my patch series next week, including some AMD implementation (not the entire AMD pipeline yet). We're also adding a 1D_LUT type that's much simpler, basically a copy of what the drm_crtc currently uses. One option is to keep both types, another is to see if AMD's LUT can be expressed using the caps that you define. I think it should be possible to express it as a single segment. There might be another few changes in the core that might help you. Like seeing the value of the client cap in the driver. It's really good to see your work. With that we'll have three driver implementations: VKMS, Intel, AMD,, which shows broad usability of this approach. Harry > 2. Implement pipe color management (post blending) based on the current > color pipeline design. > 3. Work with compositor maintainers to get color processing implemented > using display hardware, thereby avoid any GL or GPU shaders. > > Thanks to all the community maintainers and contributors who have helped > to get this support in upstream Linux. Looking forward to collaborate, > work together and get this merged. > > Cc: Ville Syrjala <ville.syrjala@linux.intel.com> > Cc: Pekka Paalanen <pekka.paalanen@collabora.com> > Cc: Simon Ser <contact@emersion.fr> > Cc: Harry Wentland <harry.wentland@amd.com> > Cc: Melissa Wen <mwen@igalia.com> > Cc: Jonas Ådahl <jadahl@redhat.com> > Cc: Sebastian Wick <sebastian.wick@redhat.com> > Cc: Shashank Sharma <shashank.sharma@amd.com> > Cc: Alexander Goins <agoins@nvidia.com> > Cc: Joshua Ashton <joshua@froggi.es> > Cc: Michel Dänzer <mdaenzer@redhat.com> > Cc: Aleix Pol <aleixpol@kde.org> > Cc: Xaver Hugl <xaver.hugl@gmail.com> > Cc: Victoria Brekenfeld <victoria@system76.com> > Cc: Sima <daniel@ffwll.ch> > Cc: Naseer Ahmed <quic_naseer@quicinc.com> > Cc: Christopher Braga <quic_cbraga@quicinc.com> > Cc: Abhinav Kumar <quic_abhinavk@quicinc.com> > Cc: Arthur Grillo <arthurgrillo@riseup.net> > Cc: Hector Martin <marcan@marcan.st> > Cc: Liviu Dudau <Liviu.Dudau@arm.com> > Cc: Sasha McIntosh <sashamcintosh@google.com> > Cc: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com> > > Chaitanya Kumar Borah (16): > drm: Add missing function declarations > drm: handle NULL next colorop in drm_colorop_set_next_property > drm: Fix error logging in set Color Pipeline > drm: Add support for 3x3 CTM > drm: Add 1D LUT color op > drm/i915: Add identifiers for intel color blocks > drm/i915: Add intel_color_op > drm/i915/color: Add helper to allocate intel colorop > drm/i915/color: Add helper to create intel colorop > drm/i915/color: Create a transfer function color pipeline > drm/i915/color: Add and attach COLORPIPELINE plane property > drm/i915/color: Add framework to set colorop > drm/i915/color: Add callbacks to set plane CTM > drm/i915/color: Add framework to program PRE/POST CSC LUT > FIXME: force disable legacy plane color properties for TGL and beyond > drm/i915/color: Enable Plane Color Pipelines > > Harry Wentland (1): > [NOT FOR REVIEW] drm: color pipeline base work > > Uma Shankar (11): > drm: Add Enhanced LUT precision structure > drm: Add Color lut range attributes > drm: Add Color ops capability property > drm: Define helper to create color ops capability property > drm: Define helper for adding capability property for 1D LUT > drm/i915: Define segmented Lut and add capabilities to colorop > drm/i915/color: Add plane CTM callback for TGL and beyond > drm/i915: Add register definitions for Plane Degamma > drm/i915: Add register definitions for Plane Post CSC > drm/i915/color: Program Pre-CSC registers > drm/i915/xelpd: Program Plane Post CSC Registers > > Documentation/gpu/rfc/color_pipeline.rst | 352 ++++++++ > drivers/gpu/drm/Makefile | 1 + > drivers/gpu/drm/drm_atomic.c | 147 ++++ > drivers/gpu/drm/drm_atomic_helper.c | 12 + > drivers/gpu/drm/drm_atomic_state_helper.c | 5 + > drivers/gpu/drm/drm_atomic_uapi.c | 170 ++++ > drivers/gpu/drm/drm_colorop.c | 335 ++++++++ > drivers/gpu/drm/drm_ioctl.c | 7 + > drivers/gpu/drm/drm_mode_config.c | 7 + > drivers/gpu/drm/i915/display/intel_color.c | 562 ++++++++++++ > drivers/gpu/drm/i915/display/intel_color.h | 16 + > .../drm/i915/display/intel_display_limits.h | 13 + > .../drm/i915/display/intel_display_types.h | 17 + > .../drm/i915/display/skl_universal_plane.c | 19 +- > drivers/gpu/drm/i915/i915_reg.h | 124 +++ > drivers/gpu/drm/tests/Makefile | 4 +- > drivers/gpu/drm/tests/drm_fixp_test.c | 69 ++ > drivers/gpu/drm/vkms/Kconfig | 5 + > drivers/gpu/drm/vkms/Makefile | 4 +- > drivers/gpu/drm/vkms/tests/.kunitconfig | 4 + > drivers/gpu/drm/vkms/tests/vkms_color_tests.c | 355 ++++++++ > drivers/gpu/drm/vkms/vkms_colorop.c | 115 +++ > drivers/gpu/drm/vkms/vkms_composer.c | 117 ++- > drivers/gpu/drm/vkms/vkms_drv.h | 8 + > drivers/gpu/drm/vkms/vkms_luts.c | 802 ++++++++++++++++++ > drivers/gpu/drm/vkms/vkms_luts.h | 12 + > drivers/gpu/drm/vkms/vkms_plane.c | 2 + > include/drm/drm_atomic.h | 87 ++ > include/drm/drm_atomic_uapi.h | 3 + > include/drm/drm_color_mgmt.h | 23 + > include/drm/drm_colorop.h | 274 ++++++ > include/drm/drm_file.h | 7 + > include/drm/drm_fixed.h | 18 + > include/drm/drm_mode_config.h | 18 + > include/drm/drm_plane.h | 10 + > include/uapi/drm/drm.h | 18 + > include/uapi/drm/drm_mode.h | 83 ++ > 37 files changed, 3815 insertions(+), 10 deletions(-) > create mode 100644 Documentation/gpu/rfc/color_pipeline.rst > create mode 100644 drivers/gpu/drm/drm_colorop.c > create mode 100644 drivers/gpu/drm/tests/drm_fixp_test.c > create mode 100644 drivers/gpu/drm/vkms/tests/.kunitconfig > create mode 100644 drivers/gpu/drm/vkms/tests/vkms_color_tests.c > create mode 100644 drivers/gpu/drm/vkms/vkms_colorop.c > create mode 100644 drivers/gpu/drm/vkms/vkms_luts.c > create mode 100644 drivers/gpu/drm/vkms/vkms_luts.h > create mode 100644 include/drm/drm_colorop.h >
> -----Original Message----- > From: Harry Wentland <harry.wentland@amd.com> > Sent: Saturday, February 17, 2024 3:17 AM > To: Shankar, Uma <uma.shankar@intel.com>; intel-gfx@lists.freedesktop.org; dri- > devel@lists.freedesktop.org > Cc: ville.syrjala@linux.intel.com; pekka.paalanen@collabora.com; > contact@emersion.fr; mwen@igalia.com; jadahl@redhat.com; > sebastian.wick@redhat.com; shashank.sharma@amd.com; agoins@nvidia.com; > joshua@froggi.es; mdaenzer@redhat.com; aleixpol@kde.org; > xaver.hugl@gmail.com; victoria@system76.com; daniel@ffwll.ch; > quic_naseer@quicinc.com; quic_cbraga@quicinc.com; > quic_abhinavk@quicinc.com; arthurgrillo@riseup.net; marcan@marcan.st; > Liviu.Dudau@arm.com; sashamcintosh@google.com; sean@poorly.run; Borah, > Chaitanya Kumar <chaitanya.kumar.borah@intel.com> > Subject: Re: [PATCH 00/28] Plane Color Pipeline support for Intel platforms > > > > On 2024-02-13 01:48, Uma Shankar wrote: > > This series intends to add support for Plane Color Management for > > Intel platforms. This is based on the design which has been agreed > > upon by the community. Series implementing the design for generic DRM > > core has been sent out by Harry Wentland and is under review > > below: > > https://patchwork.freedesktop.org/series/123446/ > > > > The base work of above series is squashed under 1 patch and support > > for Intel platform is added on top of it. > > Any reviews on the original core design is expected to be done in > > Harry's series to avoid any forking of the discussion. > > > > We have added some changes/fixes to the Harry's core DRM changes, > > being put up as separate patches on top of squashed patch. These are > > expected to get included in the main series from Harry once agreed upon. > > > > Changes added on core design: > > 1. Below patches implement some fixes on original series > > drm: Add missing function declarations > > drm: handle NULL next colorop in drm_colorop_set_next_property > > drm: Fix error logging in set Color Pipeline > > > > 2. Implemented a HW capability property to expose segmented luts. > > drm: Add Color lut range attributes > > drm: Add Color ops capability property > > drm: Define helper to create color ops capability property > > drm: Define helper for adding capability property for 1D LUT > > > > This helps in generically defining the hardware lut capabilities, lut > > distribution, precision, segmented or PWL LUTS. > > > > 3. Added support for enhanced prescision, 3x3 matrix and 1d LUT: > > drm: Add Enhanced LUT precision structure > > drm: Add support for 3x3 CTM > > drm: Add 1D LUT color op > > > > On top of this base work for DRM core plane color pipeline design, > > implementation is done for Intel hardware platforms. Below patches > > include the same: > > > > drm/i915: Add identifiers for intel color blocks > > drm/i915: Add intel_color_op > > drm/i915/color: Add helper to allocate intel colorop > > drm/i915/color: Add helper to create intel colorop > > drm/i915/color: Create a transfer function color pipeline > > drm/i915/color: Add and attach COLORPIPELINE plane property > > drm/i915/color: Add framework to set colorop > > drm/i915/color: Add callbacks to set plane CTM > > drm/i915/color: Add framework to program PRE/POST CSC LUT > > FIXME: force disable legacy plane color properties for TGL and beyond > > drm/i915/color: Enable Plane Color Pipelines > > drm/i915: Define segmented Lut and add capabilities to colorop > > drm/i915/color: Add plane CTM callback for TGL and beyond > > drm/i915: Add register definitions for Plane Degamma > > drm/i915: Add register definitions for Plane Post CSC > > drm/i915/color: Program Pre-CSC registers > > drm/i915/xelpd: Program Plane Post CSC Registers > > > > Bhanu from Intel will be sending out the igt changes to help test the > > color pipeline implementation based on the current igt changes sent > > out by Harry. > > https://patchwork.freedesktop.org/series/123448/ > > > > Planned Next Steps: > > 1. Work with Harry and community and get DRM core changes for color > > pipeline merged. > > We'll need a userspace to implement support before merging, but we're working > to enabling all color properties gamescope currently uses for the SteamDeck color > management to the Color Pipeline API, which should help us get there. It's still a > journey but I think the path is clear. Yeah, thanks Harry for driving it. > I'll send a new version of my patch series next week, including some AMD > implementation (not the entire AMD pipeline yet). Oh ok, Nice. One more input which can be considered: Currently this is plane level color management (pre blending), can we make names of function also like that ? We can later work on pipe level color (post blending) on top of it without any major rework. Eventually this support will be needed for post blending as well (current properties will fall short on modern hardware). > We're also adding a 1D_LUT type that's much simpler, basically a copy of what the > drm_crtc currently uses. One option is to keep both types, another is to see if > AMD's LUT can be expressed using the caps that you define. I think it should be > possible to express it as a single segment. Yes, I believe it will be simple on AMD h/w to just add 1 segment with number of luts. This way we can generalize it for all multi segmented LUT usecases (like on Intel), this anyways will be needed as we currently don't have any way to expose these to userspace. > There might be another few changes in the core that might help you. Like seeing > the value of the client cap in the driver. Sure, we were also thinking that client caps may be useful. Will check your changes. > It's really good to see your work. With that we'll have three driver > implementations: VKMS, Intel, AMD,, which shows broad usability of this > approach. Surely this is a good step. We are step by step reaching there. Thanks Harry and all others who have helped to get this far. Regards, Uma Shankar > Harry > > > 2. Implement pipe color management (post blending) based on the > > current color pipeline design. > > 3. Work with compositor maintainers to get color processing > > implemented using display hardware, thereby avoid any GL or GPU shaders. > > > > Thanks to all the community maintainers and contributors who have > > helped to get this support in upstream Linux. Looking forward to > > collaborate, work together and get this merged. > > > > Cc: Ville Syrjala <ville.syrjala@linux.intel.com> > > Cc: Pekka Paalanen <pekka.paalanen@collabora.com> > > Cc: Simon Ser <contact@emersion.fr> > > Cc: Harry Wentland <harry.wentland@amd.com> > > Cc: Melissa Wen <mwen@igalia.com> > > Cc: Jonas Ådahl <jadahl@redhat.com> > > Cc: Sebastian Wick <sebastian.wick@redhat.com> > > Cc: Shashank Sharma <shashank.sharma@amd.com> > > Cc: Alexander Goins <agoins@nvidia.com> > > Cc: Joshua Ashton <joshua@froggi.es> > > Cc: Michel Dänzer <mdaenzer@redhat.com> > > Cc: Aleix Pol <aleixpol@kde.org> > > Cc: Xaver Hugl <xaver.hugl@gmail.com> > > Cc: Victoria Brekenfeld <victoria@system76.com> > > Cc: Sima <daniel@ffwll.ch> > > Cc: Naseer Ahmed <quic_naseer@quicinc.com> > > Cc: Christopher Braga <quic_cbraga@quicinc.com> > > Cc: Abhinav Kumar <quic_abhinavk@quicinc.com> > > Cc: Arthur Grillo <arthurgrillo@riseup.net> > > Cc: Hector Martin <marcan@marcan.st> > > Cc: Liviu Dudau <Liviu.Dudau@arm.com> > > Cc: Sasha McIntosh <sashamcintosh@google.com> > > Cc: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com> > > > > Chaitanya Kumar Borah (16): > > drm: Add missing function declarations > > drm: handle NULL next colorop in drm_colorop_set_next_property > > drm: Fix error logging in set Color Pipeline > > drm: Add support for 3x3 CTM > > drm: Add 1D LUT color op > > drm/i915: Add identifiers for intel color blocks > > drm/i915: Add intel_color_op > > drm/i915/color: Add helper to allocate intel colorop > > drm/i915/color: Add helper to create intel colorop > > drm/i915/color: Create a transfer function color pipeline > > drm/i915/color: Add and attach COLORPIPELINE plane property > > drm/i915/color: Add framework to set colorop > > drm/i915/color: Add callbacks to set plane CTM > > drm/i915/color: Add framework to program PRE/POST CSC LUT > > FIXME: force disable legacy plane color properties for TGL and beyond > > drm/i915/color: Enable Plane Color Pipelines > > > > Harry Wentland (1): > > [NOT FOR REVIEW] drm: color pipeline base work > > > > Uma Shankar (11): > > drm: Add Enhanced LUT precision structure > > drm: Add Color lut range attributes > > drm: Add Color ops capability property > > drm: Define helper to create color ops capability property > > drm: Define helper for adding capability property for 1D LUT > > drm/i915: Define segmented Lut and add capabilities to colorop > > drm/i915/color: Add plane CTM callback for TGL and beyond > > drm/i915: Add register definitions for Plane Degamma > > drm/i915: Add register definitions for Plane Post CSC > > drm/i915/color: Program Pre-CSC registers > > drm/i915/xelpd: Program Plane Post CSC Registers > > > > Documentation/gpu/rfc/color_pipeline.rst | 352 ++++++++ > > drivers/gpu/drm/Makefile | 1 + > > drivers/gpu/drm/drm_atomic.c | 147 ++++ > > drivers/gpu/drm/drm_atomic_helper.c | 12 + > > drivers/gpu/drm/drm_atomic_state_helper.c | 5 + > > drivers/gpu/drm/drm_atomic_uapi.c | 170 ++++ > > drivers/gpu/drm/drm_colorop.c | 335 ++++++++ > > drivers/gpu/drm/drm_ioctl.c | 7 + > > drivers/gpu/drm/drm_mode_config.c | 7 + > > drivers/gpu/drm/i915/display/intel_color.c | 562 ++++++++++++ > > drivers/gpu/drm/i915/display/intel_color.h | 16 + > > .../drm/i915/display/intel_display_limits.h | 13 + > > .../drm/i915/display/intel_display_types.h | 17 + > > .../drm/i915/display/skl_universal_plane.c | 19 +- > > drivers/gpu/drm/i915/i915_reg.h | 124 +++ > > drivers/gpu/drm/tests/Makefile | 4 +- > > drivers/gpu/drm/tests/drm_fixp_test.c | 69 ++ > > drivers/gpu/drm/vkms/Kconfig | 5 + > > drivers/gpu/drm/vkms/Makefile | 4 +- > > drivers/gpu/drm/vkms/tests/.kunitconfig | 4 + > > drivers/gpu/drm/vkms/tests/vkms_color_tests.c | 355 ++++++++ > > drivers/gpu/drm/vkms/vkms_colorop.c | 115 +++ > > drivers/gpu/drm/vkms/vkms_composer.c | 117 ++- > > drivers/gpu/drm/vkms/vkms_drv.h | 8 + > > drivers/gpu/drm/vkms/vkms_luts.c | 802 ++++++++++++++++++ > > drivers/gpu/drm/vkms/vkms_luts.h | 12 + > > drivers/gpu/drm/vkms/vkms_plane.c | 2 + > > include/drm/drm_atomic.h | 87 ++ > > include/drm/drm_atomic_uapi.h | 3 + > > include/drm/drm_color_mgmt.h | 23 + > > include/drm/drm_colorop.h | 274 ++++++ > > include/drm/drm_file.h | 7 + > > include/drm/drm_fixed.h | 18 + > > include/drm/drm_mode_config.h | 18 + > > include/drm/drm_plane.h | 10 + > > include/uapi/drm/drm.h | 18 + > > include/uapi/drm/drm_mode.h | 83 ++ > > 37 files changed, 3815 insertions(+), 10 deletions(-) create mode > > 100644 Documentation/gpu/rfc/color_pipeline.rst > > create mode 100644 drivers/gpu/drm/drm_colorop.c create mode 100644 > > drivers/gpu/drm/tests/drm_fixp_test.c > > create mode 100644 drivers/gpu/drm/vkms/tests/.kunitconfig > > create mode 100644 drivers/gpu/drm/vkms/tests/vkms_color_tests.c > > create mode 100644 drivers/gpu/drm/vkms/vkms_colorop.c > > create mode 100644 drivers/gpu/drm/vkms/vkms_luts.c create mode > > 100644 drivers/gpu/drm/vkms/vkms_luts.h create mode 100644 > > include/drm/drm_colorop.h > >