From patchwork Tue Feb 20 14:20:32 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andi Shyti X-Patchwork-Id: 13564093 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 4F403C48BC3 for ; Tue, 20 Feb 2024 14:21:09 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 7D44E10E45F; Tue, 20 Feb 2024 14:21:05 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="fGciVtlV"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.21]) by gabe.freedesktop.org (Postfix) with ESMTPS id 7012B10E45A; Tue, 20 Feb 2024 14:21:03 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1708438864; x=1739974864; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=s28gQVWPZGE3H1osjrzS3iQPjQBdB6vAoufDHgxlyXs=; b=fGciVtlVx+m8Xvqwe318uhPw6FW1Yxqu+E0ILs4yEiiiShXXdyUKZVCV +tbPwmR1t5s+6/Qgg63k1gExa+LS7lYvvkGQ5uk6Lmt3GVlUDeXqXbhhz R+7YV3rePdEA5bTF8VZvolGouISrJ38rJbOF4YpMGFM+9o9/JcIQC2TGM AujacErnau5shqMxvaSYc05Xam+TDI1+LJHJHF/d8nMX31QJJhgdVWxKJ NC9KOXfn9OCDPDnClFR44sDHaS+1NfBjm/oAP+dAqERPezfrxd8f8qZDS tGZZ9jl9y0FKH4mmjFFkVSvpv2TU9uoXURsFVJ7ibFY0uYM0ta+6W+MgV g==; X-IronPort-AV: E=McAfee;i="6600,9927,10989"; a="2447022" X-IronPort-AV: E=Sophos;i="6.06,172,1705392000"; d="scan'208";a="2447022" Received: from orviesa001.jf.intel.com ([10.64.159.141]) by orvoesa113.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Feb 2024 06:21:03 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.06,172,1705392000"; d="scan'208";a="42283459" Received: from alichtma-mobl.ger.corp.intel.com (HELO intel.com) ([10.246.34.74]) by smtpauth.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Feb 2024 06:21:00 -0800 From: Andi Shyti To: intel-gfx , dri-devel Cc: Chris Wilson , Joonas Lahtinen , Matt Roper , John Harrison , Tvrtko Ursulin , stable@vger.kernel.org, Andi Shyti , Andi Shyti Subject: [PATCH 0/2] Disable automatic load CCS load balancing Date: Tue, 20 Feb 2024 15:20:32 +0100 Message-ID: <20240220142034.257370-1-andi.shyti@linux.intel.com> X-Mailer: git-send-email 2.43.0 MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Hi, this series does basically two things: 1. Disables automatic load balancing as adviced by the hardware workaround. 2. Forces the sharing of the load submitted to CCS among all the CCS available (as of now only DG2 has more than one CCS). This way the user, when sending a query, will see only one CCS available. Andi Andi Shyti (2): drm/i915/gt: Disable HW load balancing for CCS drm/i915/gt: Set default CCS mode '1' drivers/gpu/drm/i915/gt/intel_gt.c | 11 +++++++++++ drivers/gpu/drm/i915/gt/intel_gt_regs.h | 3 +++ drivers/gpu/drm/i915/gt/intel_workarounds.c | 6 ++++++ drivers/gpu/drm/i915/i915_drv.h | 17 +++++++++++++++++ drivers/gpu/drm/i915/i915_query.c | 5 +++-- 5 files changed, 40 insertions(+), 2 deletions(-)