From patchwork Fri Nov 1 06:27:21 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Jouni_H=C3=B6gander?= X-Patchwork-Id: 13858773 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id DEE7FE674A7 for ; Fri, 1 Nov 2024 06:27:50 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 5060310E216; Fri, 1 Nov 2024 06:27:50 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="G00buVKi"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.13]) by gabe.freedesktop.org (Postfix) with ESMTPS id ECB8710E1BB; Fri, 1 Nov 2024 06:27:48 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1730442469; x=1761978469; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=membmhDCeha2zvBfRl6Rc3/Z/FrM51fgKWu7HBM3IMA=; b=G00buVKiinVIziPKF/nFC+Fir7fd3YL8lrHjdZnC4UZnmFtrzvckUcbV 2jqXaH49d669+g3CCJ1+ge1zD13r0lejCA8Mk7YksFK5hxduf+3HAQ0OL +PqZ8/VUAYMH0RUV9i/HfVh3WGZVWq8rTnUtes+emmkYGgQHynLm8Z/Og qZxjvYz6bOWqaSZVxf8mh85U93p7TvS0YfRLHA24CvZpo5eyL6nlX4VGj iX+GaUw4eq6CfxtlwReQw4iOHxgdcv9dQI8swiEbpZ3vFBT8C5IFBtS+y /Y0kaSq0ar88vf88FuBhUrVwxILjebEOQi4MWuqNU5vt6G7Lzce5HYWXM A==; X-CSE-ConnectionGUID: MxMvcGAYQDa9J4FsJC6V0Q== X-CSE-MsgGUID: OyGtraAOQ1CX6T05+QLayw== X-IronPort-AV: E=McAfee;i="6700,10204,11222"; a="41306057" X-IronPort-AV: E=Sophos;i="6.11,199,1725346800"; d="scan'208";a="41306057" Received: from orviesa003.jf.intel.com ([10.64.159.143]) by orvoesa105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 31 Oct 2024 23:27:49 -0700 X-CSE-ConnectionGUID: C9V7i+B5SY6IcjfnKMJcQQ== X-CSE-MsgGUID: 3i24X6cHQb2AirPV5jZvyA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.11,199,1725346800"; d="scan'208";a="87648562" Received: from ksztyber-mobl2.ger.corp.intel.com (HELO jhogande-mobl1..) ([10.245.244.3]) by ORVIESA003-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 31 Oct 2024 23:27:47 -0700 From: =?utf-8?q?Jouni_H=C3=B6gander?= To: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org Cc: =?utf-8?q?Jouni_H=C3=B6gander?= Subject: [PATCH v2 0/7] Use trans push mechanism to generate frame change event Date: Fri, 1 Nov 2024 08:27:21 +0200 Message-Id: <20241101062728.3865980-1-jouni.hogander@intel.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Currently we are using "automatic" frame change event generation. The event is generated by any access to plane or pipe registers. We have option to use "PSR PR Frame Change Enable" bit in TRANS_PUSH register to enable frame change event generation on trans push. When this bit is set "automatic" frame change event generation doesn't work anymore. This patch set is taking trans push mechanism into use. NOTE: Patches add vrr.trans_push_enabled into intel_crtc and stores trans push vrr and psr enable bits in trans_push_enabled. There is no need for additional locking as it's taken care by psr mutex. v2: implement intel_vrr_trans_push_enabled_set_clear and use that instead of rmw Jouni Högander (7): drm/i915/psr: Add TRANS_PUSH register bit definition for PSR drm/i915/vrr: Do not overwrite TRANS_PUSH PSR Frame Change Enable drm/i915/vrr: Use TRANS_PUSH mechanism for PSR frame change drm/i915/psr: Rename psr_force_hw_tracking_exit as psr_force_exit drm/i915/psr: Simplify frontbuffer invalidate/flush callbacks drm/i915/psr: Add VRR send push interface for PSR usage drm/i915/display: Generate PSR frame change event on cursor update drivers/gpu/drm/i915/display/intel_cursor.c | 5 ++ .../drm/i915/display/intel_display_types.h | 2 + drivers/gpu/drm/i915/display/intel_psr.c | 83 ++++++------------- drivers/gpu/drm/i915/display/intel_vrr.c | 81 ++++++++++++++++-- drivers/gpu/drm/i915/display/intel_vrr.h | 6 ++ drivers/gpu/drm/i915/display/intel_vrr_regs.h | 1 + 6 files changed, 115 insertions(+), 63 deletions(-)