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[0/2] SSC enablement in port clock programming

Message ID 20250106040821.251114-1-suraj.kandpal@intel.com (mailing list archive)
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Series SSC enablement in port clock programming | expand

Message

Kandpal, Suraj Jan. 6, 2025, 4:08 a.m. UTC 
According to specs SSC is enabled during port clock programming based on
below conditions:
-if uhbr 10 or uhbr 20 enable ssc regardless of what display controller
asks of us
-if ubhr 13.5 or legacy rates enable ssc if required.
Currently these conditions are not exactly followed this patch series
fixes that.
One more thing this patch addresses is how SSC was not enabled for c20
PHY at all because ssc_enabled variable is never set for c20 PHY.

Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>

Suraj Kandpal (2):
  drm/i915/cx0: Fix SSC enablement in PORT_CLOCK_CTL
  drm/i915/cx0: Set ssc_enabled for c20 too

 drivers/gpu/drm/i915/display/intel_cx0_phy.c | 18 ++++++++++++++----
 1 file changed, 14 insertions(+), 4 deletions(-)