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([10.245.245.185]) by fmviesa007-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Jan 2025 23:31:57 -0800 From: =?utf-8?q?Jouni_H=C3=B6gander?= To: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org Cc: =?utf-8?q?Jouni_H=C3=B6gander?= Subject: [PATCH v3 00/10] PSR DSB support Date: Thu, 9 Jan 2025 09:31:27 +0200 Message-ID: <20250109073137.1977494-1-jouni.hogander@intel.com> X-Mailer: git-send-email 2.43.0 MIME-Version: 1.0 Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" This patch set is doing necessary modifications to support PSR update using DSB on LunarLake onwards It is not necessary to wait for PSR1 to idle or PSR2 to exit DEEP sleep at the begin of commit This is left out from DSB commit. There might be room for optimization for non-DSB as well because such wait is not supposed to be necessary at the begin of update. PSR mutex is not locked when performing DSB commit. It is not necessary as we are currently using DSB only when sending updates towards panel. I.e. not using it when changing PSR mode. Also necessary changes are made to use PSR2_MAN_TRK_CTL only in DSB. Frontbuffer updates and legacy cursor updates are using SFF_CTL register to perform full frame updates. DSB_SKIP_WAITS_EN is kept set as otherwise DSB wait for scanline hangs if it's entered when PSR2_STATUS[PSR2 State] == DEEP_SLEEP or SRD_STATUS[SRD State] == SRDENT. v3: - do not use DSB when PSR mode is changing v2: - use _MMIO_TRANS instead of _MMIO_TRANS2 - drop evasion from intel_psr_configure_full_frame_update Jouni Högander (10): drm/i915/psr: Use PSR2_MAN_TRK_CTL CFF bit only to send full update drm/i915/psr: Rename psr_force_hw_tracking_exit as intel_psr_force_update drm/i915/psr: Split setting sff and cff bits away from intel_psr_force_update drm/i915/psr: Add register definitions for SFF_CTL and CFF_CTL registers drm/i915/psr: Use SFF_CTL on invalidate/flush for LunarLake onwards drm/i915/psr: Allow writing PSR2_MAN_TRK_CTL using DSB drm/i915/psr: Changes for PSR2_MAN_TRK_CTL handling when DSB is in use drm/i915/psr: Add intel_psr_is_psr_mode_changing drm/i915/display: Don't use DSB if psr mode changing drm/i915/psr: Allow DSB usage when PSR is enabled drivers/gpu/drm/i915/display/intel_display.c | 11 +- drivers/gpu/drm/i915/display/intel_psr.c | 139 +++++++++--------- drivers/gpu/drm/i915/display/intel_psr.h | 6 +- drivers/gpu/drm/i915/display/intel_psr_regs.h | 10 ++ 4 files changed, 95 insertions(+), 71 deletions(-)