[0/4] Panel Replay mode change without full modeset

Message

Jouni Högander Jan. 9, 2025, 10:35 a.m. UTC

This patch set allows changing Panel Replay mode without full
modeset. There are couple of requirements in eDP1.5/DP2.0 spec:

"Enabling of the PR function shall occur prior to link training. To
re-enable the PR function after the PR function is disabled, it is
necessary to repeat link training."

This is achieved by enabling Panel Replay before link training always
if Panel Replay is supported by both sink and source. Panel Replay
enable bit is never cleared on sink side. When we are disabling Panel
Replay we are just disabling it on source side. This triggers sending
"VSC SDP" with "PR_STATE" set as "0 = PR Inactive (normal operation
mode, Live Frame mode)"

"The Source device may enable Selective Update by setting DPCD
001B0h[6] = 1 prior to transmitting a VSC SDP with the PR Active state
indication (DB1[0] = 1). The Source device that enables PR SU with
ALPM shall enable SU Region Early Transport by setting DPCD 001B0h[7]
= 1 prior to transmitting a VSC SDP with DB1[0] = 1."

These are achieved by transiting to Panel Replay Inactive state before
changing Selective Update or Early Transport bits.

Jouni Högander (4):
  drm/i915/psr: Add new function for writing sink panel replay enable
    bit
  drm/i915/psr: Enable Panel Replay on sink always when it's supported
  drm/i915/psr: Make intel_psr_enable_sink as local static function
  drm/i915/psr: Allow changing Panel Replay mode without full modeset

 drivers/gpu/drm/i915/display/intel_ddi.c     |  3 +-
 drivers/gpu/drm/i915/display/intel_display.c | 14 --------
 drivers/gpu/drm/i915/display/intel_psr.c     | 36 ++++++++++++++------
 drivers/gpu/drm/i915/display/intel_psr.h     |  3 +-
 4 files changed, 28 insertions(+), 28 deletions(-)