Show patches with: Submitter = Chauhan, Madhav       |    State = Action Required       |   195 patches
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Patch Series A/R/T S/W/F Date Submitter Delegate State
[v2,05/20] drm/i915/icl: Define PORT_CL_DW_10 register - 1 - --- 2018-07-03 Chauhan, Madhav New
[v2,04/20] drm/i915/icl: Enable DSI IO power - - - --- 2018-07-03 Chauhan, Madhav New
[v2,03/20] drm/i915/icl: Define DSI mode ctl register - 1 - --- 2018-07-03 Chauhan, Madhav New
[v2,02/20] drm/i915/icl: Program DSI Escape clock Divider - - - --- 2018-07-03 Chauhan, Madhav New
[v2,01/20] drm/i915/icl: Define register for DSI PLL - 1 - --- 2018-07-03 Chauhan, Madhav New
[20/20] drm/i915/icl: Configure DSI transcoders - - - --- 2018-06-15 Chauhan, Madhav New
[19/20] drm/i915/icl: Define TRANS_DSI_FUNC_CONF register - - - --- 2018-06-15 Chauhan, Madhav New
[18/20] drm/i915/icl: Add macros for MMIO of DSI transcoder registers - - - --- 2018-06-15 Chauhan, Madhav New
[17/20] drm/i915/icl: Get DSI transcoder for a given port - - - --- 2018-06-15 Chauhan, Madhav New
[16/20] drm/i915/icl: Program TA_TIMING_PARAM registers - - - --- 2018-06-15 Chauhan, Madhav New
[15/20] drm/i915/icl: Define TA_TIMING_PARAM registers - - - --- 2018-06-15 Chauhan, Madhav New
[14/20] drm/i915/icl: Program DSI clock and data lane timing params - - - --- 2018-06-15 Chauhan, Madhav New
[13/20] drm/i915/icl: Define data/clock lanes dphy timing registers - - - --- 2018-06-15 Chauhan, Madhav New
[12/20] drm/i915/icl: Program T_INIT_MASTER registers - - - --- 2018-06-15 Chauhan, Madhav New
[11/20] drm/i915/icl: Define T_INIT_MASTER registers - - - --- 2018-06-15 Chauhan, Madhav New
[10/20] drm/i915/icl: Enable DDI Buffer - - - --- 2018-06-15 Chauhan, Madhav New
[09/20] drm/i915/icl: DSI vswing programming sequence - - - --- 2018-06-15 Chauhan, Madhav New
[08/20] drm/i915/icl: Configure lane sequencing of combo phy transmitter - - - --- 2018-06-15 Chauhan, Madhav New
[07/20] drm/i915/icl: Define AUX lane registers for Port A/B - - - --- 2018-06-15 Chauhan, Madhav New
[06/20] drm/i915/icl: Power down unused DSI lanes - 1 - --- 2018-06-15 Chauhan, Madhav New
[05/20] drm/i915/icl: Define PORT_CL_DW_10 register - - - --- 2018-06-15 Chauhan, Madhav New
[04/20] drm/i915/icl: Enable DSI IO power - - - --- 2018-06-15 Chauhan, Madhav New
[03/20] drm/i915/icl: Define DSI mode ctl register - 1 - --- 2018-06-15 Chauhan, Madhav New
[02/20] drm/i915/icl: Program DSI Escape clock Divider - - - --- 2018-06-15 Chauhan, Madhav New
[01/20] drm/i915/icl: Define register for DSI PLL - 1 - --- 2018-06-15 Chauhan, Madhav New
[2/2] drm/i915: Use existing DSI backlight ports info - 2 - --- 2017-10-13 Chauhan, Madhav New
[1/2] drm/i915: Parse DSI backlight/cabc ports. - 1 - --- 2017-10-13 Chauhan, Madhav New
[2/2] drm/i915: Use existing DSI backlight ports info - 1 - --- 2017-10-11 Chauhan, Madhav New
[1/2] drm/i915: Parse DSI backlight/cabc ports. - - - --- 2017-10-11 Chauhan, Madhav New
[2/2] drm/i915: Use existing DSI backlight ports info - 1 - --- 2017-10-03 Chauhan, Madhav New
[1/2] drm/i915: Parse DSI backlight/cabc ports. - - - --- 2017-10-03 Chauhan, Madhav New
[2/2] drm/i915/: Use existing DSI backlight ports info - - - --- 2017-10-03 Chauhan, Madhav New
[2/2] drm/i915/glk: Add cold boot sequence for GLK DSI - - - --- 2017-06-13 Chauhan, Madhav New
[1/2] drm/i915/glk: Split GLK DSI device ready functionality - - - --- 2017-06-13 Chauhan, Madhav New
drm/i915/glk: Enable cold boot for GLK DSI - - - --- 2017-06-04 Chauhan, Madhav New
[2/2] drm/i915/glk: Enable cold boot for GLK DSI - - - --- 2017-05-09 Chauhan, Madhav New
[1/2] drm/i915/glk: Calculate high/low switch count for GLK - - - --- 2017-05-09 Chauhan, Madhav New
[2/2] drm/i915/glk: Enable cold boot for GLK DSI - - - --- 2017-05-08 Chauhan, Madhav New
[1/2] drm/i915/glk: Calculate high/low switch count for GLK - - - --- 2017-05-08 Chauhan, Madhav New
drm/i915/glk: limit pixel clock to 99% of cdclk workaround - 1 - --- 2017-04-05 Chauhan, Madhav New
drm/i915/glk: CDCLK calculation changes for glk - - - --- 2017-03-20 Chauhan, Madhav New
drm/i915/glk: Fix DSI enable I/O sequence - - - --- 2017-03-01 Chauhan, Madhav New
[GLK,MIPI,DSI,V7] drm/i915/glk: Add MIPIIO Enable/disable sequence - - - --- 2017-03-01 Chauhan, Madhav New
[GLK,MIPI,DSI,V6,7/7] drm/i915/glk: Validate only DSI PORT A PLL divider - - - --- 2017-02-17 Chauhan, Madhav New
[GLK,MIPI,DSI,V6,6/7] drm/i915/glk: Program txesc clock divider for GLK - - - --- 2017-02-17 Chauhan, Madhav New
[GLK,MIPI,DSI,V6,5/7] drm/i915i/glk: Program MIPI_CLOCK_CTRL only for BXT - 1 - --- 2017-02-17 Chauhan, Madhav New
[GLK,MIPI,DSI,V6,4/7] drm/i915/glk: Add DSI PLL divider range for glk - - - --- 2017-02-17 Chauhan, Madhav New
[GLK,MIPI,DSI,V6,3/7] drm/i915/glk: Add MIPIIO Enable/disable sequence - - - --- 2017-02-17 Chauhan, Madhav New
[GLK,MIPI,DSI,V6,2/7] drm/i915/glk: Program new MIPI DSI PHY registers for GLK - 1 - --- 2017-02-17 Chauhan, Madhav New
[GLK,MIPI,DSI,V6,1/7] drm/i915/glk: Program dphy param reg for GLK - 1 - --- 2017-02-17 Chauhan, Madhav New
drm/i915/glk: CDCLK calculation changes for glk - - - --- 2017-02-16 Chauhan, Madhav New
[GLK,MIPI,DSI,V5,8/8] drm/i915/glk: Validate only DSI PORT A PLL divider - - - --- 2017-02-14 Chauhan, Madhav New
[GLK,MIPI,DSI,V5,7/8] drm/i915/glk: Program txesc clock divider for GLK - - - --- 2017-02-14 Chauhan, Madhav New
[GLK,MIPI,DSI,V5,6/8] drm/i915i/glk: Program MIPI_CLOCK_CTRL only for BXT - 1 - --- 2017-02-14 Chauhan, Madhav New
[GLK,MIPI,DSI,V5,5/8] drm/i915/glk: Add DSI PLL divider range for glk - - - --- 2017-02-14 Chauhan, Madhav New
[GLK,MIPI,DSI,V5,4/8] drm/i915: Set the Z inversion overlap field - - - --- 2017-02-14 Chauhan, Madhav New
[GLK,MIPI,DSI,V5,3/8] drm/i915/glk: Add MIPIIO Enable/disable sequence - - - --- 2017-02-14 Chauhan, Madhav New
[GLK,MIPI,DSI,V5,2/8] drm/i915/glk: Program new MIPI DSI PHY registers for GLK - 1 - --- 2017-02-14 Chauhan, Madhav New
[GLK,MIPI,DSI,V5,1/8] drm/i915/glk: Program dphy param reg for GLK - 1 - --- 2017-02-14 Chauhan, Madhav New
[GLK,MIPI,DSI,V4,8/8] drm/i915/glk: Validate only DSI PORT A PLL divider - - - --- 2017-02-07 Chauhan, Madhav New
[GLK,MIPI,DSI,V4,7/8] drm/i915/glk: Program txesc clock divider for GLK - - - --- 2017-02-07 Chauhan, Madhav New
[GLK,MIPI,DSI,V4,6/8] drm/i915i/glk: Program MIPI_CLOCK_CTRL only for BXT - - - --- 2017-02-07 Chauhan, Madhav New
[GLK,MIPI,DSI,V4,5/8] drm/i915/glk: Add DSI PLL divider range for glk - - - --- 2017-02-07 Chauhan, Madhav New
[GLK,MIPI,DSI,V4,4/8] drm/i915: Set the Z inversion overlap field - - - --- 2017-02-07 Chauhan, Madhav New
[GLK,MIPI,DSI,V4,3/8] drm/i915/glk: Add MIPIIO Enable/disable sequence - - - --- 2017-02-07 Chauhan, Madhav New
[GLK,MIPI,DSI,V4,2/8] drm/i915/glk: Program new MIPI DSI PHY registers for GLK - - - --- 2017-02-07 Chauhan, Madhav New
[GLK,MIPI,DSI,V4,1/8] drm/i915/glk: Program dphy param reg for GLK - - - --- 2017-02-07 Chauhan, Madhav New
drm/i915/glk: CDCLK calculation changes for glk - - - --- 2017-02-07 Chauhan, Madhav New
[GLK,MIPI,DSI,V3,7/7] drm/i915/glk: Program txesc clock divider for GLK - - - --- 2017-01-02 Chauhan, Madhav New
[GLK,MIPI,DSI,V3,6/7] drm/i915i/glk: Program MIPI_CLOCK_CTRL only for BXT - - - --- 2017-01-02 Chauhan, Madhav New
[GLK,MIPI,DSI,V3,5/7] drm/i915/glk: Add DSI PLL divider range for glk - - - --- 2017-01-02 Chauhan, Madhav New
[GLK,MIPI,DSI,V3,4/7] drm/i915: Set the Z inversion overlap field - - - --- 2017-01-02 Chauhan, Madhav New
[GLK,MIPI,DSI,V3,3/7] drm/i915/glk: Add MIPIIO Enable/disable sequence - - - --- 2017-01-02 Chauhan, Madhav New
[GLK,MIPI,DSI,V3,2/7] drm/i915/glk: Program new MIPI DSI PHY registers for GLK - - - --- 2017-01-02 Chauhan, Madhav New
[GLK,MIPI,DSI,V3,1/7] drm/i915/glk: Program dphy param reg for GLK - - - --- 2017-01-02 Chauhan, Madhav New
drm/915: Parsing the missed out DTD fields from the VBT - - - --- 2016-12-22 Chauhan, Madhav New
drm/915: Parsing the missed out DTD fields from the VBT - 1 - --- 2016-12-22 Chauhan, Madhav New
[GLK,MIPI,DSI,V2,9/9] drm/915: Parsing the missed out DTD fields from the VBT - - - --- 2016-12-15 Chauhan, Madhav New
[GLK,MIPI,DSI,V2,8/9] drm/i915/glk: Program dphy param reg for GLK - - - --- 2016-12-15 Chauhan, Madhav New
[GLK,MIPI,DSI,V2,7/9] drm/i915/glk: Program txesc clock divider for GLK - - - --- 2016-12-15 Chauhan, Madhav New
[GLK,MIPI,DSI,V2,6/9] drm/i915i/glk: Program MIPI_CLOCK_CTRL only for BXT - - - --- 2016-12-15 Chauhan, Madhav New
[GLK,MIPI,DSI,V2,5/9] drm/i915/glk: Add DSI PLL divider range for glk - - - --- 2016-12-15 Chauhan, Madhav New
[GLK,MIPI,DSI,V2,4/9] drm/i915: Set the Z inversion overlap field - - - --- 2016-12-15 Chauhan, Madhav New
[GLK,MIPI,DSI,V2,3/9] drm/i915/glk: Add MIPIIO Enable/disable sequence - - - --- 2016-12-15 Chauhan, Madhav New
[GLK,MIPI,DSI,V2,2/9] drm/i915/glk: Program new MIPI DSI PHY registers for GLK - - - --- 2016-12-15 Chauhan, Madhav New
[GLK,MIPI,DSI,V2,1/9] drm/i915/glk: Add new bit fields in MIPI CTRL register - - - --- 2016-12-15 Chauhan, Madhav New
[GLK,MIPI,DSI,V1,9/9] drm/915: Parsing the missed out DTD fields from the VBT - - - --- 2016-12-08 Chauhan, Madhav New
[GLK,MIPI,DSI,V1,8/9] drm/i915/glk: Program dphy param reg for GLK - - - --- 2016-12-08 Chauhan, Madhav New
[GLK,MIPI,DSI,V1,7/9] drm/i915/glk: Program txesc clock divider for GLK - - - --- 2016-12-08 Chauhan, Madhav New
[GLK,MIPI,DSI,V1,6/9] drm/i915/glk: Program MIPI_CLOCK_CTRL only for BXT - - - --- 2016-12-08 Chauhan, Madhav New
[GLK,MIPI,DSI,V1,5/9] drm/i915/glk: Add DSI PLL divider range for glk - - - --- 2016-12-08 Chauhan, Madhav New
[GLK,MIPI,DSI,V1,4/9] drm/i915: Set the Z inversion overlap field - - - --- 2016-12-08 Chauhan, Madhav New
[GLK,MIPI,DSI,V1,3/9] drm/i915/glk: Add MIPIIO Enable/disable sequence - - - --- 2016-12-08 Chauhan, Madhav New
[GLK,MIPI,DSI,V1,2/9] drm/i915/glk: Program new MIPI DSI PHY registers for GLK - - - --- 2016-12-08 Chauhan, Madhav New
[GLK,MIPI,DSI,V1,1/9] drm/i915/glk: Add new bit fields in MIPI CTRL register - - - --- 2016-12-08 Chauhan, Madhav New
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