Show patches with: State = Action Required       |   118969 patches
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Patch Series A/R/T S/W/F Date Submitter Delegate State
[3/3] uxa: Fix load_cursor_argb for the new Xorg ABI. - - - --- 2014-04-09 Eric Anholt New
[2/3] Use fbpict.h instead of defining its prototypes ourselves. - - - --- 2014-04-09 Eric Anholt New
[1/3] Update for glamor in the 1.16 server. - - - --- 2014-04-09 Eric Anholt New
drm/i915: get power domain in case the BIOS enabled eDP VDD - - - --- 2014-04-09 Paulo Zanoni New
[4/4] drm/i915: extract intel_pll.c from intel_display.c - - - --- 2014-04-09 Paulo Zanoni New
[3/4] drm/i915: extract intel_fdi.c from intel_display.c - - - --- 2014-04-09 Paulo Zanoni New
[2/4] drm/i915: extract intel_cursor.c from intel_display.c - - - --- 2014-04-09 Paulo Zanoni New
[1/4] drm/i915: extract intel_eld.c from intel_display.c - - - --- 2014-04-09 Paulo Zanoni New
drm/i915/bdw: Use timeout mode for RC6 on bdw - - - --- 2014-04-09 Tom.O'Rourke@intel.com New
[v9,10/71] drm/i915/chv: Preliminary interrupt support for Cherryview - - - --- 2014-04-09 Ville Syrjälä New
SQUASH: drm/i915: One more register for mesa - - - --- 2014-04-09 bradley.d.volkin@intel.com New
[v5,13/71] drm/i915/chv: Add Cherryview PCI IDs - - - --- 2014-04-09 Ville Syrjälä New
drm/i915: Remove spurious semicolons - - - --- 2014-04-09 Lespiau, Damien New
[2/2] drm/i915: do not setup backlight if not available according to VBT - - - --- 2014-04-09 Jani Nikula New
[1/2] drm/i915: check VBT for supported backlight type - - - --- 2014-04-09 Jani Nikula New
[71/71] drm/i915/chv: Handle video DIP registers on CHV - - - --- 2014-04-09 Ville Syrjälä New
[70/71] drm/i915: Don't use pipe_offset stuff for DPLL registers - - - --- 2014-04-09 Ville Syrjälä New
[69/71] drm/i915/chv: Force PHY clock buffers off after PLL disable - - - --- 2014-04-09 Ville Syrjälä New
[68/71] drm/i915/chv: Force clock buffer enables - - - --- 2014-04-09 Ville Syrjälä New
[67/71] drm/i915/chv: Try to program the PHY used clock channel overrides - - - --- 2014-04-09 Ville Syrjälä New
[66/71] drm/i915/chv: Use RMW to toggle swing calc init - - - --- 2014-04-09 Ville Syrjälä New
[65/71] drm/i915/chv: Don't do group access reads from TX lanes either - - - --- 2014-04-09 Ville Syrjälä New
[64/71] drm/i915/chv: Don't use PCS group access reads - - - --- 2014-04-09 Ville Syrjälä New
[63/71] drm/i915/chv: Set soft reset override bit for data lane resets - - - --- 2014-04-09 Ville Syrjälä New
[62/71] drm/i915/chv: Reset data lanes in encoder .post_disable() hook - - - --- 2014-04-09 Ville Syrjälä New
[61/71] drm/i915/chv: Turn off dclkp after the PLL has been disabled - - - --- 2014-04-09 Ville Syrjälä New
[60/71] drm/i915/chv: Move data lane deassert to encoder pre_enable - - - --- 2014-04-09 Ville Syrjälä New
[59/71] drm/i915/chv: Fix CHV PLL state tracking - - - --- 2014-04-09 Ville Syrjälä New
[58/71] drm/i915/chv: Register port D encoders and connectors - - - --- 2014-04-09 Ville Syrjälä New
[57/71] drm/i915/chv: Fix PORT_TO_PIPE for CHV - - - --- 2014-04-09 Ville Syrjälä New
[56/71] drm/i915/chv: Bump num_pipes to 3 - - - --- 2014-04-09 Ville Syrjälä New
[55/71] drm/i915/chv: Add cursor pipe offsets - - - --- 2014-04-09 Ville Syrjälä New
[54/71] drm/i915/chv: Fix gmbus for port D - - - --- 2014-04-09 Ville Syrjälä New
[53/71] drm/i915/chv: Configure crtc_mask correctly for CHV - - - --- 2014-04-09 Ville Syrjälä New
[52/71] drm/i915/chv: Make CHV irq handler loop until all interrupts are consumed - - - --- 2014-04-09 Ville Syrjälä New
[51/71] drm/i915/chv: Use valleyview_pipestat_irq_handler() for CHV - - - --- 2014-04-09 Ville Syrjälä New
[50/71] drm/i915/chv: Clarify VLV/CHV PIPESTAT bits a bit more - - - --- 2014-04-09 Ville Syrjälä New
[49/71] drm/i915/chv: Add CHV display support - - - --- 2014-04-09 Ville Syrjälä New
[48/71] drm/i915/chv: Add plane C support - - - --- 2014-04-09 Ville Syrjälä New
[47/71] drm/i915/chv: Skip gen6_gt_check_fifodbg() on CHV - - - --- 2014-04-09 Ville Syrjälä New
[46/71] drm/i915/chv: CHV doesn't need WaRsForcewakeWaitTC0 - - - --- 2014-04-09 Ville Syrjälä New
[45/71] drm/i915/chv: Streamline CHV forcewake stuff - - - --- 2014-04-09 Ville Syrjälä New
[44/71] drm/i915/chv: Fix for decrementing fw count in chv read/write. - - - --- 2014-04-09 Ville Syrjälä New
[43/71] drm/i915/chv: Add a bunch of pre production workarounds - - - --- 2014-04-09 Ville Syrjälä New
[42/71] drm/i915/chv: Implement WaDisableSamplerPowerBypass for CHV - - - --- 2014-04-09 Ville Syrjälä New
[41/71] drm/i915/chv: Add some workaround notes - - - --- 2014-04-09 Ville Syrjälä New
[40/71] drm/i915/chv: Implement WaDisableSDEUnitClockGating:chv - - - --- 2014-04-09 Ville Syrjälä New
[39/71] drm/i915/chv: Implement WaDisableCSUnitClockGating:chv - - - --- 2014-04-09 Ville Syrjälä New
[38/71] drm/i915/chv: Implement WaDisableSemaphoreAndSyncFlipWait:chv - - - --- 2014-04-09 Ville Syrjälä New
[37/71] drm/i915/chv: Implement WaVSRefCountFullforceMissDisable:chv and WaDSRefCountFullforceMissD… - - - --- 2014-04-09 Ville Syrjälä New
[36/71] drm/i915/chv: Implement WaDisableThreadStallDopClockGating:chv - - - --- 2014-04-09 Ville Syrjälä New
[35/71] drm/i915/chv: Implement WaDisablePartialInstShootdown:chv - - - --- 2014-04-09 Ville Syrjälä New
[34/71] drm/i915/chv: Implement stolen memory size detection - - - --- 2014-04-09 Ville Syrjälä New
[33/71] drm/i915/chv: Fix for verifying PCBR address field. - - - --- 2014-04-09 Ville Syrjälä New
[32/71] drm/i915/bdw: Add BDW PM Interrupts support and BDW rps disable - - - --- 2014-04-09 Ville Syrjälä New
[31/71] drm/i915/chv: Added CHV specific DDR fetch into init_clock_gating - - - --- 2014-04-09 Ville Syrjälä New
[30/71] drm/i915/chv: Enable PM interrupts when we in CHV turbo initialize sequence. - - - --- 2014-04-09 Ville Syrjälä New
[29/71] drm/i915/chv: Enable RPS (Turbo) for Cheeryview - - - --- 2014-04-09 Ville Syrjälä New
[28/71] drm/i915/chv: Added CHV specific register read and write - - - --- 2014-04-09 Ville Syrjälä New
[27/71] drm/i915/chv: Enable Render Standby (RC6) for Cheeryview - - - --- 2014-04-09 Ville Syrjälä New
[26/71] drm/i915: Enable PM Interrupts for CHV/BDW Platform. - - - --- 2014-04-09 Ville Syrjälä New
[25/71] drm/i915/chv: CHV doesn't have CRT output - - - --- 2014-04-09 Ville Syrjälä New
[24/71] drm/i915/chv: Add DPLL state readout support - - - --- 2014-04-09 Ville Syrjälä New
[23/71] drm/i915/chv: Pipe select change for DP and HDMI - - - --- 2014-04-09 Ville Syrjälä New
[22/71] drm/i915/chv: Add phy supports for Cherryview - - - --- 2014-04-09 Ville Syrjälä New
[21/71] drm/i915/chv: Add update and enable pll for Cherryview - - - --- 2014-04-09 Ville Syrjälä New
[20/71] drm/i915/chv: find the best divisor for the target clock v4 - - - --- 2014-04-09 Ville Syrjälä New
[19/71] drm/i915/chv: Trigger phy common lane reset - - - --- 2014-04-09 Ville Syrjälä New
[18/71] drm/i915/chv: Add vlv_pipe_to_channel - - - --- 2014-04-09 Ville Syrjälä New
[17/71] drm/i915/chv: Update Cherryview DPLL changes to support Port D. v2 - - - --- 2014-04-09 Ville Syrjälä New
[16/71] drm/i915/chv: Add DPIO offset for Cherryview. v3 - - - --- 2014-04-09 Ville Syrjälä New
[15/71] drm/i915/chv: Add DDL register defines for Cherryview - - - --- 2014-04-09 Ville Syrjälä New
[14/71] drm/i915/chv: Add early quirk for stolen - - - --- 2014-04-09 Ville Syrjälä New
[13/71] drm/i915/chv: Add Cherryview PCI IDs - - - --- 2014-04-09 Ville Syrjälä New
[12/71] drm/i915/chv: Initial clock gating support for Cherryview - - - --- 2014-04-09 Ville Syrjälä New
[11/71] drm/i915/chv: Add Cherryview interrupt registers into debugfs - - - --- 2014-04-09 Ville Syrjälä New
[10/71] drm/i915/chv: Preliminary interrupt support for Cherryview - - - --- 2014-04-09 Ville Syrjälä New
[09/71] drm/i915/chv: Add DPINVGTT registers defines for Cherryview - - - --- 2014-04-09 Ville Syrjälä New
[08/71] drm/i915/chv: Add display interrupt registers bits for Cherryview - - - --- 2014-04-09 Ville Syrjälä New
[07/71] drm/i915/chv: Add DPFLIPSTAT register bits for Cherryview - - - --- 2014-04-09 Ville Syrjälä New
[06/71] drm/i915/chv: Add PIPESTAT register bits for Cherryview - - - --- 2014-04-09 Ville Syrjälä New
[05/71] drm/i915/chv: Enable aliasing PPGTT for CHV - - - --- 2014-04-09 Ville Syrjälä New
[04/71] drm/i915/chv: Flush caches when programming page tables - - - --- 2014-04-09 Ville Syrjälä New
[03/71] drm/i915/chv: PPAT setup for Cherryview - - - --- 2014-04-09 Ville Syrjälä New
[02/71] drm/i915/chv: Add IS_CHERRYVIEW() macro - - - --- 2014-04-09 Ville Syrjälä New
[01/71] drm/i915/chv: IS_BROADWELL() should not be true for Cherryview - - - --- 2014-04-09 Ville Syrjälä New
[7/7] drm/i915: Enable RANDOM resolution support for MIPI panels - - - --- 2014-04-09 Kumar, Shobhit New
[6/7] drm/i915: Send DPI command explicitely in LP mode - - - --- 2014-04-09 Kumar, Shobhit New
[5/7] drm/i915: Panel commands can be sent only when clock is in LP11 - - - --- 2014-04-09 Kumar, Shobhit New
[4/7] drm/i915: Parameterize the Clockstop and escape_clk_div - - - --- 2014-04-09 Kumar, Shobhit New
[3/7] drm/i915: Disable DPOunit clock gating - - - --- 2014-04-09 Kumar, Shobhit New
[2/7] drm/i915: Enable MIPI port before the plane and pipe enable - - - --- 2014-04-09 Kumar, Shobhit New
[1/7] drm/i915: Program Rcomp and band gap reset everytime we resume from power gate - - - --- 2014-04-09 Kumar, Shobhit New
[6/6] drm/i915: Kick start the rings - - - --- 2014-04-09 Chris Wilson New
[5/6] drm/i915: Include a little more information about why ring init fails - - - --- 2014-04-09 Chris Wilson New
[4/6] drm/i915: Mark device as wedged if we fail to resume - - - --- 2014-04-09 Chris Wilson New
[3/6] drm/i915: Allow the module to load even if we fail to setup rings - - - --- 2014-04-09 Chris Wilson New
[2/6] drm/i915: Preserve ring buffers objects across resume - - - --- 2014-04-09 Chris Wilson New
[1/6] drm/i915: Replace hardcoded cacheline size with macro - - - --- 2014-04-09 Chris Wilson New
drm/i915: Always use kref tracking for all contexts. - - - --- 2014-04-09 Chris Wilson New
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