Show patches with: State = Action Required       |   89336 patches
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Patch Series A/R/T S/W/F Date Submitter Delegate State
[5/9] drm/i915: Setup EDP PSR AUX Registers - - - --- 2013-01-30 Rodrigo Vivi New
[4/9] drm/i915: Read the EDP DPCD and PSR Capability - - - --- 2013-01-30 Rodrigo Vivi New
[3/9] drm/i915: Added SDP and VSC structures for handling PSR for eDP - - - --- 2013-01-30 Rodrigo Vivi New
[2/9] drm/i915: Use cpu_transcoder for HSW_TVIDEO_DIP_* instead of pipe - - - --- 2013-01-30 Rodrigo Vivi New
[1/9] drm/i915: Organize VBT stuff inside drm_i915_private - - - --- 2013-01-30 Rodrigo Vivi New
[2/2] drm/i915: kill cargo-culted locking from power well code - - - --- 2013-01-30 Daniel Vetter New
[1/2] drm/i915: don't run hsw power well code on !hsw - - - --- 2013-01-30 Daniel Vetter New
[i-g-t,2/2] kms_flip: Add flip-vs-modeset-vs-hang test - - - --- 2013-01-30 Ville Syrjälä New
[i-g-t,1/2] kms_flip: Make flip events optional - - - --- 2013-01-30 Ville Syrjälä New
drm/i915: Increase the RC6p threshold. - - - --- 2013-01-30 Stéphane Marchesin New
drm/i915: Fix CAGF for HSW - - - --- 2013-01-29 Ben Widawsky New
[3/3] drm/i915: clear the FPGA_DBG_RM_NOCLAIM bit at driver init - - - --- 2013-01-29 Paulo Zanoni New
[3/3] drm/i915: dynamic Haswell display power well support - - - --- 2013-01-29 Paulo Zanoni New
[2/3] drm/i915: check the power down well on assert_pipe() - - - --- 2013-01-29 Paulo Zanoni New
[1/3] drm/i915: don't send DP "idle" pattern before "normal" on HSW PORT_A - - - --- 2013-01-29 Paulo Zanoni New
[6/6] drm/i915: Really wait for pending flips in intel_pipe_set_base() - - - --- 2013-01-29 Ville Syrjälä New
[5/6] drm/i915: Add intel_crtc_wait_for_pending_flips_locked() - - - --- 2013-01-29 Ville Syrjälä New
[4/6] drm/i915: Move intel_crtc_has_pending_flip() earlier - - - --- 2013-01-29 Ville Syrjälä New
[3/6] drm/i915: Wake up pending_flip_queue as part of reset handling - - - --- 2013-01-29 Ville Syrjälä New
[2/6] drm/i915: Don't wait for page flips if there was GPU reset - - - --- 2013-01-29 Ville Syrjälä New
[1/6] drm/i915: Kill obj->pending_flip - - - --- 2013-01-29 Ville Syrjälä New
[2/2] drm/i915: Adding a warning to FBC description - - - --- 2013-01-28 Ben Widawsky New
[1/2] drm/i915: Error state should print /sys/kernel/debug - - - --- 2013-01-28 Ben Widawsky New
[5/5] drm/i915: Dynamically calculate dclv - - - --- 2013-01-28 Ben Widawsky New
[4/5,v2] drm/i915: Aliased PPGTT size abstraction - - - --- 2013-01-28 Ben Widawsky New
Adding a i915 quirk (here: pipe A force quirk for testing purposes)? - - - --- 2013-01-28 Sedat Dilek New
[RFC,3/3] i915: ignore lid open event when resuming - - - --- 2013-01-27 Zhang, Rui New
[RFC,2/3] ACPI: enable ACPI SCI during suspend - - - --- 2013-01-27 Zhang, Rui New
[RFC,1/3] PM: Introduce suspend state PM_SUSPEND_FREEZE - - - --- 2013-01-27 Zhang, Rui New
drm/i915: Implement WaVSRefCountFullforceMissDisable - - - --- 2013-01-26 Ben Widawsky New
[5/5] drm/i915: Dynamically calculate dclv - - - --- 2013-01-26 Ben Widawsky New
[4/5] drm/i915: Aliased PPGTT size abstraction - - - --- 2013-01-26 Ben Widawsky New
[3/5] drm/i915: Extract gen6 aliasing ppgtt code - - - --- 2013-01-26 Ben Widawsky New
[2/5] drm/i915: Reclaim GTT space for failed PPGTT - - - --- 2013-01-26 Ben Widawsky New
[1/5] drm/i915: trivial: kill-agp collateral cleanups - - - --- 2013-01-26 Ben Widawsky New
[7/7] drm/i915: print Gen 7 error interrupts - - - --- 2013-01-25 Paulo Zanoni New
[6/7] drm/i915: only check for unclaimed registers if drm_debug - - - --- 2013-01-25 Paulo Zanoni New
[5/7] drm/i915: WARN on unclaimed registers - - - --- 2013-01-25 Paulo Zanoni New
[4/7] drm/i915: check for unclaimed registers on I915_READ too - - - --- 2013-01-25 Paulo Zanoni New
[3/7] drm/i915: clear the FPGA_DBG_RM_NOCLAIM bit at driver init - - - --- 2013-01-25 Paulo Zanoni New
[2/7] drm/i915: use FPGA_DBG for the "unclaimed register" checks - - - --- 2013-01-25 Paulo Zanoni New
[1/7] drm/i915: create macros for the "unclaimed register" checks - - - --- 2013-01-25 Paulo Zanoni New
[9/9] drm/i915: Don't touch VGA0/VGA1/VGA_PD on ILK+ - - - --- 2013-01-25 Ville Syrjälä New
[8/9] drm/i915: Set the SR01 "screen off" bit in i915_redisable_vga() too - - - --- 2013-01-25 Ville Syrjälä New
[7/9] drm/i915: Kill IS_DISPLAYREG() - - - --- 2013-01-25 Ville Syrjälä New
[6/9] drm/i915: Introduce i915_vgacntrl_reg() - - - --- 2013-01-25 Ville Syrjälä New
[5/9] drm/i915: Include display_mmio_offset in sequencer index/data registers - - - --- 2013-01-25 Ville Syrjälä New
[v2,4/9] drm/i915: Pass VLV_DISPLAY_BASE + reg to intel_{hdmi, dp}_init on VLV - - - --- 2013-01-25 Ville Syrjälä New
[3/9] drm/i915: VLV doesn't have SDVO - - - --- 2013-01-25 Ville Syrjälä New
[2/9] drm/i915: Always use adpa_reg - - - --- 2013-01-25 Ville Syrjälä New
[v2,1/9] drm/i915: PLL registers need an offset on VLV - - - --- 2013-01-25 Ville Syrjälä New
[7/7] drm/i915: set TRANSCODER_EDP even earlier - - - --- 2013-01-25 Paulo Zanoni New
[6/7] drm/i915: turn on the power well before suspending - - - --- 2013-01-25 Paulo Zanoni New
[5/7] drm/i915: check the power down well on assert_pipe() - - - --- 2013-01-25 Paulo Zanoni New
[4/7] drm/i915: only disable enabled planes on intel_fb_restore_mode - - - --- 2013-01-25 Paulo Zanoni New
[3/7] drm/i915: dynamic Haswell display power well support - - - --- 2013-01-25 Paulo Zanoni New
[2/7] drm/i915: fix intel_init_power_wells - - - --- 2013-01-25 Paulo Zanoni New
[1/7] drm/i915: don't send DP idle pattern before normal pattern on HSW - - - --- 2013-01-25 Paulo Zanoni New
[4/4] drm/i915: move DP save/restore into i915_ums.c - - - --- 2013-01-25 Daniel Vetter New
[3/4] drm/i915: dont save/restore VGA state for kms - - - --- 2013-01-25 Daniel Vetter New
[2/4] drm/i915: extract ums suspend/resume into i915_ums.c - - - --- 2013-01-25 Daniel Vetter New
[1/4] drm/i915: move modeset checks out of save/restore_modeset_reg - - - --- 2013-01-25 Daniel Vetter New
[6/6] drm/i915: Resume dissecting intel_gtt - - - --- 2013-01-24 Ben Widawsky New
[5/6] drm/i915: Add probe and remove to the gtt ops - - - --- 2013-01-24 Ben Widawsky New
[4/6] drm/i915: extract hw ppgtt setup/cleanup code - - - --- 2013-01-24 Ben Widawsky New
[3/6] drm/i915: pte_encode is gen6+ - - - --- 2013-01-24 Ben Widawsky New
[2/6] drm/i915: vfuncs for ppgtt - - - --- 2013-01-24 Ben Widawsky New
[1/6] drm/i915: vfuncs for gtt_clear_range/insert_entries - - - --- 2013-01-24 Ben Widawsky New
[6/6] drm/i915: Resume dissecting intel_gtt - - - --- 2013-01-24 Ben Widawsky New
[5/6] drm/i915: Add probe and remove to the gtt ops - - - --- 2013-01-24 Ben Widawsky New
[4/6] drm/i915: extract hw ppgtt setup/cleanup code - - - --- 2013-01-24 Ben Widawsky New
[3/6] drm/i915: pte_encode is gen6+ - - - --- 2013-01-24 Ben Widawsky New
[2/6] drm/i915: vfuncs for ppgtt - - - --- 2013-01-24 Ben Widawsky New
[1/6] drm/i915: vfuncs for gtt_clear_range/insert_entries - - - --- 2013-01-24 Ben Widawsky New
[4/4] drm/i915: extract hw ppgtt setup/cleanup code - - - --- 2013-01-24 Daniel Vetter New
[3/4] drm/i915: pte_encode is gen6+ - - - --- 2013-01-24 Daniel Vetter New
[2/4] drm/i915: vfuncs for ppgtt - - - --- 2013-01-24 Daniel Vetter New
[1/4] drm/i915: vfuncs for gtt_clear_range/insert_entries - - - --- 2013-01-24 Daniel Vetter New
[33/33] drm/i915: Kill VLV specific interrupts registers - - - --- 2013-01-24 Ville Syrjälä New
[32/33] drm/i915: Kill IS_DISPLAYREG() - - - --- 2013-01-24 Ville Syrjälä New
[31/33] drm/i915: Set display_mmio_offset for VLV - - - --- 2013-01-24 Ville Syrjälä New
[30/33] drm/i915: GPIO/GMBUS registers need an offset on VLV - - - --- 2013-01-24 Ville Syrjälä New
[29/33] drm/i915: VGA registers need an offset on VLV - - - --- 2013-01-24 Ville Syrjälä New
[28/33] drm/i915: DPIO registers are VLV only and need an offset - - - --- 2013-01-24 Ville Syrjälä New
[27/33] drm/i915: Spell out VLV_DISPLAY_BASE for interrupt registers - - - --- 2013-01-24 Ville Syrjälä New
[26/33] drm/i915: Make VLV_GUNIT_CLOCK_GATE register value more readable - - - --- 2013-01-24 Ville Syrjälä New
[25/33] drm/i915: PLL and clock gating registers need an offset on VLV - - - --- 2013-01-24 Ville Syrjälä New
[24/33] drm/i915: VLV doesn't seem to have VGA0/VGA1/VGA_PD registers - - - --- 2013-01-24 Ville Syrjälä New
[23/33] drm/i915: FB_BLC_SELF_VLV is VLV only and needs an offset - - - --- 2013-01-24 Ville Syrjälä New
[22/33] drm/i915: Pipe palette registers need an offset on VLV - - - --- 2013-01-24 Ville Syrjälä New
[21/33] drm/i915: Pipe timing registers need an offset on VLV - - - --- 2013-01-24 Ville Syrjälä New
[20/33] drm/i915: VLV_ADPA must be used in VLV code - - - --- 2013-01-24 Ville Syrjälä New
[19/33] drm/i915: PORT_HOTPLUG registers need an offset on VLV - - - --- 2013-01-24 Ville Syrjälä New
[18/33] drm/i915: Panel fitter registers need an offset on VLV - - - --- 2013-01-24 Ville Syrjälä New
[17/33] drm/i915: Pass VLV_DISPLAY_BASE + reg to intel_init_{sdvo, hdmi, dp} on VLV - - - --- 2013-01-24 Ville Syrjälä New
[16/33] drm/i915: DPFLIPSTAT and DPINVGTT registers are VLV only and need an offset - - - --- 2013-01-24 Ville Syrjälä New
[15/33] drm/i915: DSPARB register needs an offset on VLV - - - --- 2013-01-24 Ville Syrjälä New
[14/33] drm/i915: DSPFW registers need an offset on VLV - - - --- 2013-01-24 Ville Syrjälä New
[13/33] drm/i915: VLV_DDL is VLV only and needs an offset - - - --- 2013-01-24 Ville Syrjälä New
[12/33] drm/i915: Cursor registers need an offset on VLV - - - --- 2013-01-24 Ville Syrjälä New
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