Show patches with: Submitter = Chauhan, Madhav       |    State = Action Required       |   195 patches
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Patch Series A/R/T S/W/F Date Submitter Delegate State
[v6,20/20] drm/i915/icl: Set max return packet size for DSI panel ICELAKE DSI DRIVER - - - --- 2018-09-16 Chauhan, Madhav New
[v6,19/20] drm/i915/icl: Define DSI panel programming registers ICELAKE DSI DRIVER - - - --- 2018-09-16 Chauhan, Madhav New
[v6,18/20] drm/i915/icl: Enable DSI transcoders ICELAKE DSI DRIVER - - - --- 2018-09-16 Chauhan, Madhav New
[v6,17/20] drm/i915/icl: Define TRANS_CONF register for DSI ICELAKE DSI DRIVER - - - --- 2018-09-16 Chauhan, Madhav New
[v6,16/20] drm/i915/icl: Configure DSI transcoder timings ICELAKE DSI DRIVER - - - --- 2018-09-16 Chauhan, Madhav New
[v6,15/20] drm/i915/icl: Define DSI transcoder timing registers ICELAKE DSI DRIVER - - - --- 2018-09-16 Chauhan, Madhav New
[v6,14/20] drm/i915/icl: Program TRANS_DDI_FUNC_CTL registers ICELAKE DSI DRIVER - - - --- 2018-09-16 Chauhan, Madhav New
[v6,13/20] drm/i915/icl: Define TRANS_DDI_FUNC_CTL DSI registers ICELAKE DSI DRIVER - - - --- 2018-09-16 Chauhan, Madhav New
[v6,12/20] drm/i915/icl: Configure DSI transcoders ICELAKE DSI DRIVER - - - --- 2018-09-16 Chauhan, Madhav New
[v6,11/20] drm/i915/icl: Define TRANS_DSI_FUNC_CONF register ICELAKE DSI DRIVER - - - --- 2018-09-16 Chauhan, Madhav New
[v6,10/20] drm/i915/icl: Add macros for MMIO of DSI transcoder registers ICELAKE DSI DRIVER - - - --- 2018-09-16 Chauhan, Madhav New
[v6,09/20] drm/i915/icl: Get DSI transcoder for a given port ICELAKE DSI DRIVER - - - --- 2018-09-16 Chauhan, Madhav New
[v6,08/20] drm/i915/icl: Program TA_TIMING_PARAM registers ICELAKE DSI DRIVER - - - --- 2018-09-16 Chauhan, Madhav New
[v6,07/20] drm/i915/icl: Define TA_TIMING_PARAM registers ICELAKE DSI DRIVER - - - --- 2018-09-16 Chauhan, Madhav New
[v6,06/20] drm/i915/icl: Program DSI clock and data lane timing params ICELAKE DSI DRIVER - - - --- 2018-09-16 Chauhan, Madhav New
[v6,05/20] drm/i915/icl: Define data/clock lanes dphy timing registers ICELAKE DSI DRIVER - - - --- 2018-09-16 Chauhan, Madhav New
[v6,04/20] drm/i915/icl: Program T_INIT_MASTER registers ICELAKE DSI DRIVER - 1 - --- 2018-09-16 Chauhan, Madhav New
[v6,03/20] drm/i915/icl: Enable DDI Buffer ICELAKE DSI DRIVER - 1 - --- 2018-09-16 Chauhan, Madhav New
[v6,02/20] drm/i915/icl: DSI vswing programming sequence ICELAKE DSI DRIVER - - - --- 2018-09-16 Chauhan, Madhav New
[v6,01/20] drm/i915/icl: Configure lane sequencing of combo phy transmitter ICELAKE DSI DRIVER - 1 - --- 2018-09-16 Chauhan, Madhav New
[12/12] drm/i915/icl: Transcoder timings for command mode ICL DSI CMD MODE - - - --- 2018-08-08 Chauhan, Madhav New
[11/12] drm/i915/icl: Send frame to DSI panel ICL DSI CMD MODE - - - --- 2018-08-08 Chauhan, Madhav New
[10/12] drm/i915/icl: Unmask/Clear DSI TE interrupts ICL DSI CMD MODE - - - --- 2018-08-08 Chauhan, Madhav New
[09/12] drm/i915/icl: DSI TE interrupt handler ICL DSI CMD MODE - - - --- 2018-08-08 Chauhan, Madhav New
[08/12] drm/i915/icl: Enable/disable TE interrupts ICL DSI CMD MODE - - - --- 2018-08-08 Chauhan, Madhav New
[07/12] drm/i915/icl: Configure TE interrupts for DSI ICL DSI CMD MODE - - - --- 2018-08-08 Chauhan, Madhav New
[06/12] drm/i915/icl: Find encoder for DSI command mode ICL DSI CMD MODE - - - --- 2018-08-08 Chauhan, Madhav New
[05/12] drm/i915/icl: Define TE interrupt related bits ICL DSI CMD MODE - - - --- 2018-08-08 Chauhan, Madhav New
[04/12] drm/i915/icl: DSI transcoder config for command mode ICL DSI CMD MODE - - - --- 2018-08-08 Chauhan, Madhav New
[03/12] drm/i915/icl: Define DSI cmd mode registers ICL DSI CMD MODE - - - --- 2018-08-08 Chauhan, Madhav New
[02/12] drm/i915/icl: Config utility pin for DSI ICL DSI CMD MODE - - - --- 2018-08-08 Chauhan, Madhav New
[01/12] drm/i915/icl: Define utility pin ctrl register bits ICL DSI CMD MODE - - - --- 2018-08-08 Chauhan, Madhav New
[v5,13/13] drm/i915/icl: Configure DSI transcoders - - - --- 2018-07-10 Chauhan, Madhav New
[v5,12/13] drm/i915/icl: Define TRANS_DSI_FUNC_CONF register - - - --- 2018-07-10 Chauhan, Madhav New
[v5,11/13] drm/i915/icl: Add macros for MMIO of DSI transcoder registers - - - --- 2018-07-10 Chauhan, Madhav New
[v5,10/13] drm/i915/icl: Get DSI transcoder for a given port - - - --- 2018-07-10 Chauhan, Madhav New
[v5,09/13] drm/i915/icl: Program TA_TIMING_PARAM registers - - - --- 2018-07-10 Chauhan, Madhav New
[v5,08/13] drm/i915/icl: Define TA_TIMING_PARAM registers - - - --- 2018-07-10 Chauhan, Madhav New
[v5,07/13] drm/i915/icl: Program DSI clock and data lane timing params - - - --- 2018-07-10 Chauhan, Madhav New
[v5,06/13] drm/i915/icl: Define data/clock lanes dphy timing registers - - - --- 2018-07-10 Chauhan, Madhav New
[v5,05/13] drm/i915/icl: Program T_INIT_MASTER registers - 1 - --- 2018-07-10 Chauhan, Madhav New
[v5,04/13] drm/i915/icl: Define T_INIT_MASTER registers - - - --- 2018-07-10 Chauhan, Madhav New
[v5,03/13] drm/i915/icl: Enable DDI Buffer - 1 - --- 2018-07-10 Chauhan, Madhav New
[v5,02/13] drm/i915/icl: DSI vswing programming sequence - - - --- 2018-07-10 Chauhan, Madhav New
[v5,01/13] drm/i915/icl: Configure lane sequencing of combo phy transmitter - 1 - --- 2018-07-10 Chauhan, Madhav New
[v4,20/20] drm/i915/icl: Configure DSI transcoders - - - --- 2018-07-05 Chauhan, Madhav New
[v4,19/20] drm/i915/icl: Define TRANS_DSI_FUNC_CONF register - - - --- 2018-07-05 Chauhan, Madhav New
[v4,18/20] drm/i915/icl: Add macros for MMIO of DSI transcoder registers - - - --- 2018-07-05 Chauhan, Madhav New
[v4,17/20] drm/i915/icl: Get DSI transcoder for a given port - - - --- 2018-07-05 Chauhan, Madhav New
[v4,16/20] drm/i915/icl: Program TA_TIMING_PARAM registers - - - --- 2018-07-05 Chauhan, Madhav New
[v4,15/20] drm/i915/icl: Define TA_TIMING_PARAM registers - - - --- 2018-07-05 Chauhan, Madhav New
[v4,14/20] drm/i915/icl: Program DSI clock and data lane timing params - - - --- 2018-07-05 Chauhan, Madhav New
[v4,13/20] drm/i915/icl: Define data/clock lanes dphy timing registers - - - --- 2018-07-05 Chauhan, Madhav New
[v4,12/20] drm/i915/icl: Program T_INIT_MASTER registers - - - --- 2018-07-05 Chauhan, Madhav New
[v4,11/20] drm/i915/icl: Define T_INIT_MASTER registers - - - --- 2018-07-05 Chauhan, Madhav New
[v4,10/20] drm/i915/icl: Enable DDI Buffer - - - --- 2018-07-05 Chauhan, Madhav New
[v4,09/20] drm/i915/icl: DSI vswing programming sequence - - - --- 2018-07-05 Chauhan, Madhav New
[v4,08/20] drm/i915/icl: Configure lane sequencing of combo phy transmitter - - - --- 2018-07-05 Chauhan, Madhav New
[v4,07/20] drm/i915/icl: Define AUX lane registers for Port A/B - 1 - --- 2018-07-05 Chauhan, Madhav New
[v4,06/20] drm/i915/icl: Power down unused DSI lanes - 1 - --- 2018-07-05 Chauhan, Madhav New
[v4,05/20] drm/i915/icl: Define PORT_CL_DW_10 register - 1 - --- 2018-07-05 Chauhan, Madhav New
[v4,04/20] drm/i915/icl: Enable DSI IO power - - - --- 2018-07-05 Chauhan, Madhav New
[v4,03/20] drm/i915/icl: Define DSI mode ctl register - 1 - --- 2018-07-05 Chauhan, Madhav New
[v4,02/20] drm/i915/icl: Program DSI Escape clock Divider - - - --- 2018-07-05 Chauhan, Madhav New
[v4,01/20] drm/i915/icl: Define register for DSI PLL - 1 - --- 2018-07-05 Chauhan, Madhav New
[v3,20/20] drm/i915/icl: Configure DSI transcoders - - - --- 2018-07-05 Chauhan, Madhav New
[v3,19/20] drm/i915/icl: Define TRANS_DSI_FUNC_CONF register - - - --- 2018-07-05 Chauhan, Madhav New
[v3,18/20] drm/i915/icl: Add macros for MMIO of DSI transcoder registers - - - --- 2018-07-05 Chauhan, Madhav New
[v3,17/20] drm/i915/icl: Get DSI transcoder for a given port - - - --- 2018-07-05 Chauhan, Madhav New
[v3,16/20] drm/i915/icl: Program TA_TIMING_PARAM registers - - - --- 2018-07-05 Chauhan, Madhav New
[v3,15/20] drm/i915/icl: Define TA_TIMING_PARAM registers - - - --- 2018-07-05 Chauhan, Madhav New
[v3,14/20] drm/i915/icl: Program DSI clock and data lane timing params - - - --- 2018-07-05 Chauhan, Madhav New
[v3,13/20] drm/i915/icl: Define data/clock lanes dphy timing registers - - - --- 2018-07-05 Chauhan, Madhav New
[v3,12/20] drm/i915/icl: Program T_INIT_MASTER registers - - - --- 2018-07-05 Chauhan, Madhav New
[v3,11/20] drm/i915/icl: Define T_INIT_MASTER registers - - - --- 2018-07-05 Chauhan, Madhav New
[v3,10/20] drm/i915/icl: Enable DDI Buffer - - - --- 2018-07-05 Chauhan, Madhav New
[v3,09/20] drm/i915/icl: DSI vswing programming sequence - - - --- 2018-07-05 Chauhan, Madhav New
[v3,08/20] drm/i915/icl: Configure lane sequencing of combo phy transmitter - - - --- 2018-07-05 Chauhan, Madhav New
[v3,07/20] drm/i915/icl: Define AUX lane registers for Port A/B - 1 - --- 2018-07-05 Chauhan, Madhav New
[v3,06/20] drm/i915/icl: Power down unused DSI lanes - 1 - --- 2018-07-05 Chauhan, Madhav New
[v3,05/20] drm/i915/icl: Define PORT_CL_DW_10 register - 1 - --- 2018-07-05 Chauhan, Madhav New
[v3,04/20] drm/i915/icl: Enable DSI IO power - - - --- 2018-07-05 Chauhan, Madhav New
[v3,03/20] drm/i915/icl: Define DSI mode ctl register - 1 - --- 2018-07-05 Chauhan, Madhav New
[v3,02/20] drm/i915/icl: Program DSI Escape clock Divider - - - --- 2018-07-05 Chauhan, Madhav New
[v3,01/20] drm/i915/icl: Define register for DSI PLL - 1 - --- 2018-07-05 Chauhan, Madhav New
[v2,20/20] drm/i915/icl: Configure DSI transcoders - - - --- 2018-07-03 Chauhan, Madhav New
[v2,19/20] drm/i915/icl: Define TRANS_DSI_FUNC_CONF register - - - --- 2018-07-03 Chauhan, Madhav New
[v2,18/20] drm/i915/icl: Add macros for MMIO of DSI transcoder registers - - - --- 2018-07-03 Chauhan, Madhav New
[v2,17/20] drm/i915/icl: Get DSI transcoder for a given port - - - --- 2018-07-03 Chauhan, Madhav New
[v2,16/20] drm/i915/icl: Program TA_TIMING_PARAM registers - - - --- 2018-07-03 Chauhan, Madhav New
[v2,15/20] drm/i915/icl: Define TA_TIMING_PARAM registers - - - --- 2018-07-03 Chauhan, Madhav New
[v2,14/20] drm/i915/icl: Program DSI clock and data lane timing params - - - --- 2018-07-03 Chauhan, Madhav New
[v2,13/20] drm/i915/icl: Define data/clock lanes dphy timing registers - - - --- 2018-07-03 Chauhan, Madhav New
[v2,12/20] drm/i915/icl: Program T_INIT_MASTER registers - - - --- 2018-07-03 Chauhan, Madhav New
[v2,11/20] drm/i915/icl: Define T_INIT_MASTER registers - - - --- 2018-07-03 Chauhan, Madhav New
[v2,10/20] drm/i915/icl: Enable DDI Buffer - - - --- 2018-07-03 Chauhan, Madhav New
[v2,09/20] drm/i915/icl: DSI vswing programming sequence - - - --- 2018-07-03 Chauhan, Madhav New
[v2,08/20] drm/i915/icl: Configure lane sequencing of combo phy transmitter - - - --- 2018-07-03 Chauhan, Madhav New
[v2,07/20] drm/i915/icl: Define AUX lane registers for Port A/B - 1 - --- 2018-07-03 Chauhan, Madhav New
[v2,06/20] drm/i915/icl: Power down unused DSI lanes - 1 - --- 2018-07-03 Chauhan, Madhav New
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