Show patches with: Submitter = Ville Syrjala       |    State = Action Required       |    Archived = No       |   3747 patches
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Patch Series A/R/T S/W/F Date Submitter Delegate State
[v2,01/17] drm/i915: Clean up various HPD defines - - - 0 0 0 2015-08-27 Ville Syrjala New
[3/3] drm/i915: Flatten intel_dp_check_mst_status() - - - 0 0 0 2015-08-27 Ville Syrjala New
[2/3] drm/i915: Flatten the mst suspend/resume functions a bit - - - 0 0 0 2015-08-27 Ville Syrjala New
[1/3] drm/i915: Protect MST retraining with connection_mutex - - - 0 0 0 2015-08-27 Ville Syrjala New
[6/6] drm/radeon: Send out the full AUX address - - - 0 0 0 2015-08-27 Ville Syrjala New
[5/6] drm/dp: Use I2C_WRITE_STATUS_UPDATE to drain partial I2C_WRITE requests - - - 0 0 0 2015-08-27 Ville Syrjala New
[4/6] drm/tegra: Handle I2C_WRITE_STATUS_UPDATE for address only writes - - - 0 0 0 2015-08-27 Ville Syrjala New
[3/6] drm/radeon: Handle DP_AUX_I2C_WRITE_STATUS_UPDATE - - - 0 0 0 2015-08-27 Ville Syrjala New
[2/6] drm/i915: Handle DP_AUX_I2C_WRITE_STATUS_UPDATE - - - 0 0 0 2015-08-27 Ville Syrjala New
[1/6] drm/dp: s/I2C_STATUS/I2C_WRITE_STATUS_UPDATE/ - - - 0 0 0 2015-08-27 Ville Syrjala New
[3/2] drm/i915: Factor out intel_crtc_has_encoders() - - - 0 0 0 2015-08-26 Ville Syrjala New
[v2,2/2] drm/i915: Fix clock readout when pipes are enabled w/o ports - - - 0 0 0 2015-08-26 Ville Syrjala New
[3/3] drm/i915: Make some string arrays const - - - 0 0 0 2015-08-21 Ville Syrjala New
[2/3] drm/i915: Use ARRAY_SIZE() instead of hand rolling it - - - 0 0 0 2015-08-21 Ville Syrjala New
[1/3] drm/i915: Fix some gcc warnings - - - 0 0 0 2015-08-21 Ville Syrjala New
drm/i915: Check DP link status on long hpd too - - - 0 0 0 2015-08-20 Ville Syrjala New
[12/11] drm/i915: Reinitialize HPD after runtime D3 - - - 0 0 0 2015-08-19 Ville Syrjala New
drm/i915: Try to fix MST for SKL - - - 0 0 0 2015-08-17 Ville Syrjala New
[v2] drm/i915: Put back lane_count into intel_dp and add link_rate too - - - 0 0 0 2015-08-17 Ville Syrjala New
drm/i915: Pass pipe_config to DP link training functions - - - 0 0 0 2015-08-17 Ville Syrjala New
[2/2] drm/i915: Fix clock readout when pipes are enabld w/o ports - - - 0 0 0 2015-08-13 Ville Syrjala New
[1/2] drm/i915: Assign hwmode after encoder state readout - - - 0 0 0 2015-08-13 Ville Syrjala New
[4/4] drm/i915: Make SDVO deal with HDMI pixel repeat - - - 0 0 0 2015-08-13 Ville Syrjala New
[3/4] drm/i915: Implement limited color range for SDVO properly - - - 0 0 0 2015-08-13 Ville Syrjala New
[2/4] drm/i915: Fix SDVO colorimetry bit defines - - - 0 0 0 2015-08-13 Ville Syrjala New
[1/4] drm/i915: Clean up SDVO limited color range handling - - - 0 0 0 2015-08-13 Ville Syrjala New
[11/11] drm/i915: Add port A HPD support for SPT - - - 0 0 0 2015-08-12 Ville Syrjala New
[10/11] drm/i915: Add port A HPD support for BDW - - - 0 0 0 2015-08-12 Ville Syrjala New
[09/11] drm/i915: LPT:LP needs port A HPD enabled in both north and south - - - 0 0 0 2015-08-12 Ville Syrjala New
[08/11] drm/i915: Add port A HPD support for IVB/HSW - - - 0 0 0 2015-08-12 Ville Syrjala New
[07/11] drm/i915: Add port A HPD support for ILK/SNB - - - 0 0 0 2015-08-12 Ville Syrjala New
[06/11] drm/i915: Introduce spt_irq_handler() - - - 0 0 0 2015-08-12 Ville Syrjala New
[05/11] drm/i915: Rename BXT PORTA HPD defines - - - 0 0 0 2015-08-12 Ville Syrjala New
[04/11] drm/i915: Add HAS_PCH_LPT_LP() macro - - - 0 0 0 2015-08-12 Ville Syrjala New
[03/11] drm/i915: Factor out ilk_update_display_irq() - - - 0 0 0 2015-08-12 Ville Syrjala New
[02/11] drm/i915; Extract intel_hpd_enabled_irqs() - - - 0 0 0 2015-08-12 Ville Syrjala New
[01/11] drm/i915: Clean up various HPD defines - - - 0 0 0 2015-08-12 Ville Syrjala New
[v2,2/7] drm/i915: Don't use link_bw for PLL setup - - - 0 0 0 2015-08-11 Ville Syrjala New
[i-g-t] tests/gem_pwrite_snooped: Verify set_caching vs. pwrite clflush behaviour - - - 0 0 0 2015-08-11 Ville Syrjala New
[v2] drm/i915: clflush on pin_to_display after pwrite to UC bo in LLC - - - 0 0 0 2015-08-11 Ville Syrjala New
[i-g-t] tests/kms_pwrite_crc: Use drmModeSetPlane() instead of igt_plane_set_fb() - - - 0 0 0 2015-08-11 Ville Syrjala New
drm/i915: clflush on pin_to_display after pwrite to UC bo in LLC - - - 0 0 0 2015-08-11 Ville Syrjala New
[v2,10/15] drm/i915: Force common lane on for the PPS kick on CHV - - - 0 0 0 2015-07-10 Ville Syrjala New
[v2,13/15] drm/i915: Clean up CHV lane soft reset programming - - - 0 0 0 2015-07-09 Ville Syrjala New
[15/15] drm/i915: Add CHV PHY LDO power sanity checks - - - 0 0 0 2015-07-08 Ville Syrjala New
[14/15] drm/i915: Add some CHV DPIO lane power state asserts - - - 0 0 0 2015-07-08 Ville Syrjala New
[13/15] drm/i915: Clean up CHV lane soft reset programming - - - 0 0 0 2015-07-08 Ville Syrjala New
[12/15] drm/i915: Force CL2 off in CHV x1 PHY - - - 0 0 0 2015-07-08 Ville Syrjala New
[11/15] drm/i915: Enable DPIO SUS clock gating on CHV - - - 0 0 0 2015-07-08 Ville Syrjala New
[10/15] drm/i915: Force common lane on for the PPS kick on CHV - - - 0 0 0 2015-07-08 Ville Syrjala New
[09/15] drm/i915: Trick CL2 into life on CHV when using pipe B with port B - - - 0 0 0 2015-07-08 Ville Syrjala New
[08/15] drm/i915: Implement PHY lane power gating for CHV - - - 0 0 0 2015-07-08 Ville Syrjala New
[07/15] drm/i915: Add vlv_dport_to_phy() - - - 0 0 0 2015-07-08 Ville Syrjala New
[06/15] drm/i915: Move VLV/CHV prepare_pll later - - - 0 0 0 2015-07-08 Ville Syrjala New
[05/15] drm/i915: Add locking around chv_phy_control_init() - - - 0 0 0 2015-07-08 Ville Syrjala New
[04/15] drm/i915: Move DPIO port init earlier - - - 0 0 0 2015-07-08 Ville Syrjala New
[03/15] drm/i915: Add encoder->post_pll_disable() hooks and move CHV clock buffer disables there - - - 0 0 0 2015-07-08 Ville Syrjala New
[02/15] drm/i915: Always program unique transition scale for CHV - - - 0 0 0 2015-07-08 Ville Syrjala New
[01/15] drm/i915: Always program m2 fractional value on CHV - - - 0 0 0 2015-07-08 Ville Syrjala New
[v2,5/7] drm/i915: Move intel_dp->lane_count into pipe_config - - - 0 0 0 2015-07-06 Ville Syrjala New
drm/i915: Improve DP downstream HPD handling - - - 0 0 0 2015-07-06 Ville Syrjala New
[7/7] drm/i915: Kill intel_dp->{link_bw, rate_select} - - - 0 0 0 2015-07-06 Ville Syrjala New
[6/7] drm/i915: Don't use link_bw to select between TP1 and TP3 - - - 0 0 0 2015-07-06 Ville Syrjala New
[5/7] drm/i915: Move intel_dp->lane_count into pipe_config - - - 0 0 0 2015-07-06 Ville Syrjala New
[4/7] drm/i915: Avoid confusion between DP and TRANS_DP_CTL in DP .get_config() - - - 0 0 0 2015-07-06 Ville Syrjala New
[3/7] drm/i915: Don't pass clock to DDI PLL select functions - - - 0 0 0 2015-07-06 Ville Syrjala New
[2/7] drm/i915: Don't use link_bw for PLL setup - - - 0 0 0 2015-07-06 Ville Syrjala New
[1/7] drm/i915: Clean up DP/HDMI limited color range handling - - - 0 0 0 2015-07-06 Ville Syrjala New
drm/i915: Adjust BXT HDMI port clock limits - - - 0 0 0 2015-07-06 Ville Syrjala New
drm/i915: Drop a spurious intel_pre_plane_update() call - - - 0 0 0 2015-07-03 Ville Syrjala New
drm/i915: Disable LVDS port after the pipe on PCH - - - 0 0 0 2015-07-02 Ville Syrjala New
[v2,07/10] drm/i915: Try to make sure cxsr is disabled around plane enable/disable - - - 0 0 0 2015-07-01 Ville Syrjala New
[v2,3/4] drm/i915: Account for CHV/BXT DPLL clock limitations - - - 0 0 0 2015-06-30 Ville Syrjala New
[4/4] Revert "drm/i915: Disable 12bpc hdmi for now" - - - 0 0 0 2015-06-30 Ville Syrjala New
[3/4] drm/i915: Account for CHV/BXT DPLL clock limitations - - - 0 0 0 2015-06-30 Ville Syrjala New
[2/4] drm/i915: Bump HDMI min port clock to 25 MHz - - - 0 0 0 2015-06-30 Ville Syrjala New
[1/4] drm/i915: Fix HDMI 12bpc and pixel repeat clock readout for DDI platforms - - - 0 0 0 2015-06-30 Ville Syrjala New
Revert "drm/i915: Allocate context objects from stolen" - - - 0 0 0 2015-06-29 Ville Syrjala New
[9/9] drm/i915: Disable DSI PLL before reconfiguring it - - - 0 0 0 2015-06-29 Ville Syrjala New
[8/9] drm/i915: Implement WaPixelRepeatModeFixForC0:chv - - - 0 0 0 2015-06-29 Ville Syrjala New
[7/9] drm/i915: Make {vlv, chv}_{disable, update}_pll() more similar - - - 0 0 0 2015-06-29 Ville Syrjala New
[6/9] drm/i915: Move DPLL ref/cri/VGA mode frobbing to the disp2d well enable - - - 0 0 0 2015-06-29 Ville Syrjala New
[5/9] drm/i915: Clear out DPLL state from pipe config in DSI get config - - - 0 0 0 2015-06-29 Ville Syrjala New
[4/9] drm/i915: Refactor VLV display power well init/deinit - - - 0 0 0 2015-06-29 Ville Syrjala New
[3/9] drm/i915: Simplify CHV pipe A power well code - - - 0 0 0 2015-06-29 Ville Syrjala New
[2/9] drm/i915: Apply OCD to VLV/CHV DPLL defines - - - 0 0 0 2015-06-29 Ville Syrjala New
[1/9] drm/i915: Keep GMCH DPLL VGA mode always disabled - - - 0 0 0 2015-06-29 Ville Syrjala New
[10/10] drm/i915: Zero unused WM1 watermarks on VLV/CHV - - - 0 0 0 2015-06-24 Ville Syrjala New
[09/10] drm/i915: Add debugfs knobs for VLVCHV memory latency values - - - 0 0 0 2015-06-24 Ville Syrjala New
[08/10] drm/i915: Don't do PM5/DDR DVFS with multiple pipes - - - 0 0 0 2015-06-24 Ville Syrjala New
[07/10] drm/i915: Try to make sure cxsr is disabled around plane enable/disable - - - 0 0 0 2015-06-24 Ville Syrjala New
[06/10] drm/i915: Use the memory latency based WM computation on VLV too - - - 0 0 0 2015-06-24 Ville Syrjala New
[05/10] drm/i915: Compute display FIFO split dynamically for CHV - - - 0 0 0 2015-06-24 Ville Syrjala New
[04/10] drm/i915: CHV DDR DVFS support and another watermark rewrite - - - 0 0 0 2015-06-24 Ville Syrjala New
[03/10] drm/i915: Read wm values from hardware at init on CHV - - - 0 0 0 2015-06-24 Ville Syrjala New
[02/10] drm/i915: Split atomic wm update to pre and post variants - - - 0 0 0 2015-06-24 Ville Syrjala New
[01/10] drm/i915: POSTING_READ() in intel_set_memory_cxsr() - - - 0 0 0 2015-06-24 Ville Syrjala New
[3/3] drm/i915: Don't set cursor rotate bits when cursor is disabled - - - 0 0 0 2015-06-24 Ville Syrjala New
[2/3] drm/i915: Add debug messages for pipe enable/disable - - - 0 0 0 2015-06-24 Ville Syrjala New
[1/3] drm/i915: Store frontbuffer_bits in the plane - - - 0 0 0 2015-06-24 Ville Syrjala New
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