Show patches with: Submitter = Ville Syrjala       |    Archived = No       |   114 patches
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Patch Series A/R/T S/W/F Date Submitter Delegate State
[05/18] drm/i915: Extract ilk_fb_cb_factor() drm/i915: PLL refactoring - - - --- 2024-04-12 Ville Syrjala New
[04/18] drm/i915: Introduce some local PLL state variables drm/i915: PLL refactoring - - - --- 2024-04-12 Ville Syrjala New
[03/18] drm/i915: Rename PLL hw_state variables/arguments drm/i915: PLL refactoring - - - --- 2024-04-12 Ville Syrjala New
[02/18] drm/i915: Use printer for the rest of PLL debugfs dump drm/i915: PLL refactoring - - - --- 2024-04-12 Ville Syrjala New
[01/18] drm/i915: Replace hand rolled PLL state dump with intel_dpll_dump_hw_state() drm/i915: PLL refactoring - - - --- 2024-04-12 Ville Syrjala New
[8/8] drm/i915: Enable per-lane DP drive settings for bxt/glk drm/i915: BXT/GLK per-lane vswing and PHY reg cleanup - - - --- 2024-04-12 Ville Syrjala New
[7/8] drm/i915/dpio: Program bxt/glk PHY TX registers per-lane drm/i915: BXT/GLK per-lane vswing and PHY reg cleanup - - - --- 2024-04-12 Ville Syrjala New
[6/8] drm/i915/dpio: s/ddi/dpio/ for bxt/glk PHY stuff drm/i915: BXT/GLK per-lane vswing and PHY reg cleanup - - - --- 2024-04-12 Ville Syrjala New
[5/8] drm/i915/dpio: Use intel_de_rmw() for BXT DPIO latency optim setup drm/i915: BXT/GLK per-lane vswing and PHY reg cleanup - - - --- 2024-04-12 Ville Syrjala New
[4/8] drm/i915/dpio: Introdude bxt_ddi_phy_rmw_grp() drm/i915: BXT/GLK per-lane vswing and PHY reg cleanup - - - --- 2024-04-12 Ville Syrjala New
[3/8] drm/i915/dpio: Extract bxt_dpio_phy_regs.h drm/i915: BXT/GLK per-lane vswing and PHY reg cleanup - - - --- 2024-04-12 Ville Syrjala New
[2/8] drm/i915/dpio: Add per-lane PHY TX register definitons for bxt/glk drm/i915: BXT/GLK per-lane vswing and PHY reg cleanup - - - --- 2024-04-12 Ville Syrjala New
[1/8] drm/i915/dpio: Clean up bxt/glk PHY registers drm/i915: BXT/GLK per-lane vswing and PHY reg cleanup - - - --- 2024-04-12 Ville Syrjala New
drm/edid: Parse topology block for all DispID structure v1.x drm/edid: Parse topology block for all DispID structure v1.x 1 - - --- 2024-04-10 Ville Syrjala New
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