From patchwork Tue Jun 30 07:38:24 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: sonika.jindal@intel.com X-Patchwork-Id: 6694381 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 609A09F972 for ; Tue, 30 Jun 2015 07:40:30 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 7383220520 for ; Tue, 30 Jun 2015 07:40:29 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id 72ADD2051F for ; Tue, 30 Jun 2015 07:40:27 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id BB1776E1A7; Tue, 30 Jun 2015 00:40:26 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by gabe.freedesktop.org (Postfix) with ESMTP id B40B86E1A7 for ; Tue, 30 Jun 2015 00:40:25 -0700 (PDT) Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by orsmga102.jf.intel.com with ESMTP; 30 Jun 2015 00:40:25 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.15,376,1432623600"; d="scan'208";a="753072603" Received: from pgsmsx102.gar.corp.intel.com ([10.221.44.80]) by fmsmga002.fm.intel.com with ESMTP; 30 Jun 2015 00:40:24 -0700 Received: from bgsmsx153.gar.corp.intel.com (10.224.23.4) by PGSMSX102.gar.corp.intel.com (10.221.44.80) with Microsoft SMTP Server (TLS) id 14.3.224.2; Tue, 30 Jun 2015 15:38:25 +0800 Received: from bgsmsx104.gar.corp.intel.com ([169.254.5.202]) by BGSMSX153.gar.corp.intel.com ([169.254.2.234]) with mapi id 14.03.0224.002; Tue, 30 Jun 2015 13:08:25 +0530 From: "Jindal, Sonika" To: "Kannan, Vandana" , "intel-gfx@lists.freedesktop.org" Thread-Topic: [PATCH] drm/i915/bxt: Calculate port clock Thread-Index: AQHQswcqDGPTlJuDCECzcBo2j6/Xa53EqTlg Date: Tue, 30 Jun 2015 07:38:24 +0000 Message-ID: <000C66961D35964B9714611E548C10AD0C22A3F1@BGSMSX104.gar.corp.intel.com> References: <1435651048-15716-1-git-send-email-vandana.kannan@intel.com> In-Reply-To: <1435651048-15716-1-git-send-email-vandana.kannan@intel.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [10.223.10.10] MIME-Version: 1.0 Subject: Re: [Intel-gfx] [PATCH] drm/i915/bxt: Calculate port clock X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Spam-Status: No, score=-4.8 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP I think Imre already has a patch for this: [Intel-gfx] [PATCH v2 5/5] drm/i915/bxt: add DDI port HW readout support" -----Original Message----- From: Kannan, Vandana Sent: Tuesday, June 30, 2015 1:27 PM To: intel-gfx@lists.freedesktop.org Cc: Thulasimani, Sivakumar; Jindal, Sonika; Deak, Imre; Kannan, Vandana Subject: [PATCH] drm/i915/bxt: Calculate port clock bxt_calc_pll_link() has been returning 0 all this while. This patch adds calculation in bxt_calc_pll_link() based on the chv calculation used in bxt_find_best_dpll(). Signed-off-by: Vandana Kannan --- drivers/gpu/drm/i915/i915_reg.h | 2 ++ drivers/gpu/drm/i915/intel_ddi.c | 38 ++++++++++++++++++++++++++++++++++++-- 2 files changed, 38 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index ac985c5..1d9c5dd 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -1171,8 +1171,10 @@ enum skl_disp_power_wells { #define _PORT_PLL_EBB_0_B 0x6C034 #define _PORT_PLL_EBB_0_C 0x6C340 #define PORT_PLL_P1_MASK (0x07 << 13) +#define PORT_PLL_P1_SHIFT 13 #define PORT_PLL_P1(x) ((x) << 13) #define PORT_PLL_P2_MASK (0x1f << 8) +#define PORT_PLL_P2_SHIFT 8 #define PORT_PLL_P2(x) ((x) << 8) #define BXT_PORT_PLL_EBB_0(port) _PORT3(port, _PORT_PLL_EBB_0_A, \ _PORT_PLL_EBB_0_B, \ diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c index 42c1487..a8fbcc6 100644 --- a/drivers/gpu/drm/i915/intel_ddi.c +++ b/drivers/gpu/drm/i915/intel_ddi.c @@ -968,8 +968,42 @@ static void hsw_ddi_clock_get(struct intel_encoder *encoder, static int bxt_calc_pll_link(struct drm_i915_private *dev_priv, enum intel_dpll_id dpll) { - /* FIXME formula not available in bspec */ - return 0; + enum port port = (enum port)dpll; /* 1:1 port->PLL mapping */ + uint32_t ebb0, pll0, pll2; + uint32_t m2_int, m2_frac; + intel_clock_t clock; + int refclk = 100000; + + /* + * FIXME: + * The below calculation needs to be revisited if/when + * the calculation in bxt_find_best_dpll() changes. + */ + clock.n = 1; + clock.m1 = 2; + + ebb0 = I915_READ(BXT_PORT_PLL_EBB_0(port)); + clock.p1 = (ebb0 & PORT_PLL_P1_MASK) >> PORT_PLL_P1_SHIFT; + clock.p2 = (ebb0 & PORT_PLL_P2_MASK) >> PORT_PLL_P2_SHIFT; + + pll0 = I915_READ(BXT_PORT_PLL(port, 0)); + m2_int = (pll0 & PORT_PLL_M2_MASK) << 22; + + pll2 = I915_READ(BXT_PORT_PLL(port, 2)); + m2_frac = (pll2 & PORT_PLL_M2_FRAC_MASK); + + clock.m2 = m2_int | m2_frac; + + clock.m = clock.m1 * clock.m2; + clock.p = clock.p1 * clock.p2; + if (WARN_ON(clock.n == 0 || clock.p == 0)) + return 0; + + clock.vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock.m, + clock.n << 22); + clock.dot = DIV_ROUND_CLOSEST(clock.vco, clock.p); + + return (clock.dot / 5); } static void bxt_ddi_clock_get(struct intel_encoder *encoder, -- 2.0.1