diff mbox series

[17/19] drm/i915: pass dev_priv explicitly to ALPM_CTL2

Message ID 09acf2751cfd2f524e6ba97c3ac285495eae5c86.1714471597.git.jani.nikula@intel.com (mailing list archive)
State New
Headers show
Series drm/i915/psr: implicit dev_priv removal | expand

Commit Message

Jani Nikula April 30, 2024, 10:10 a.m. UTC
Avoid the implicit dev_priv local variable use, and pass dev_priv
explicitly to the ALPM_CTL2 register macro.

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/display/intel_psr_regs.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

Comments

Rodrigo Vivi May 1, 2024, 2:25 a.m. UTC | #1
On Tue, Apr 30, 2024 at 01:10:11PM +0300, Jani Nikula wrote:
> Avoid the implicit dev_priv local variable use, and pass dev_priv
> explicitly to the ALPM_CTL2 register macro.
> 
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_psr_regs.h | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_psr_regs.h b/drivers/gpu/drm/i915/display/intel_psr_regs.h
> index 4d950b22d4f1..05dc1c1d4ac2 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr_regs.h
> +++ b/drivers/gpu/drm/i915/display/intel_psr_regs.h
> @@ -321,7 +321,7 @@
>  #define  ALPM_CTL_AUX_LESS_WAKE_TIME(val)		REG_FIELD_PREP(ALPM_CTL_AUX_LESS_WAKE_TIME_MASK, val)
>  
>  #define _ALPM_CTL2_A	0x60954
> -#define ALPM_CTL2(tran)	_MMIO_TRANS2(dev_priv, tran, _ALPM_CTL2_A)
> +#define ALPM_CTL2(dev_priv, tran)	_MMIO_TRANS2(dev_priv, tran, _ALPM_CTL2_A)

no usage? should we just delete it?

>  #define  ALPM_CTL2_SWITCH_TO_ACTIVE_LATENCY_MASK		REG_GENMASK(28, 24)
>  #define  ALPM_CTL2_SWITCH_TO_ACTIVE_LATENCY(val)		REG_FIELD_PREP(ALPM_CTL2_SWITCH_TO_ACTIVE_LATENCY_MASK, val)
>  #define  ALPM_CTL2_AUX_LESS_WAKE_TIME_EXTENSION_MASK		REG_GENMASK(19, 16)
> -- 
> 2.39.2
>
Jani Nikula May 2, 2024, 10:40 a.m. UTC | #2
On Tue, 30 Apr 2024, Rodrigo Vivi <rodrigo.vivi@intel.com> wrote:
> On Tue, Apr 30, 2024 at 01:10:11PM +0300, Jani Nikula wrote:
>> Avoid the implicit dev_priv local variable use, and pass dev_priv
>> explicitly to the ALPM_CTL2 register macro.
>> 
>> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
>> ---
>>  drivers/gpu/drm/i915/display/intel_psr_regs.h | 2 +-
>>  1 file changed, 1 insertion(+), 1 deletion(-)
>> 
>> diff --git a/drivers/gpu/drm/i915/display/intel_psr_regs.h b/drivers/gpu/drm/i915/display/intel_psr_regs.h
>> index 4d950b22d4f1..05dc1c1d4ac2 100644
>> --- a/drivers/gpu/drm/i915/display/intel_psr_regs.h
>> +++ b/drivers/gpu/drm/i915/display/intel_psr_regs.h
>> @@ -321,7 +321,7 @@
>>  #define  ALPM_CTL_AUX_LESS_WAKE_TIME(val)		REG_FIELD_PREP(ALPM_CTL_AUX_LESS_WAKE_TIME_MASK, val)
>>  
>>  #define _ALPM_CTL2_A	0x60954
>> -#define ALPM_CTL2(tran)	_MMIO_TRANS2(dev_priv, tran, _ALPM_CTL2_A)
>> +#define ALPM_CTL2(dev_priv, tran)	_MMIO_TRANS2(dev_priv, tran, _ALPM_CTL2_A)
>
> no usage? should we just delete it?

I believe a recent addition to enable ALPM. Jouni?

BR,
Jani.

>
>>  #define  ALPM_CTL2_SWITCH_TO_ACTIVE_LATENCY_MASK		REG_GENMASK(28, 24)
>>  #define  ALPM_CTL2_SWITCH_TO_ACTIVE_LATENCY(val)		REG_FIELD_PREP(ALPM_CTL2_SWITCH_TO_ACTIVE_LATENCY_MASK, val)
>>  #define  ALPM_CTL2_AUX_LESS_WAKE_TIME_EXTENSION_MASK		REG_GENMASK(19, 16)
>> -- 
>> 2.39.2
>>
Hogander, Jouni May 6, 2024, 7:34 a.m. UTC | #3
On Thu, 2024-05-02 at 13:40 +0300, Jani Nikula wrote:
> On Tue, 30 Apr 2024, Rodrigo Vivi <rodrigo.vivi@intel.com> wrote:
> > On Tue, Apr 30, 2024 at 01:10:11PM +0300, Jani Nikula wrote:
> > > Avoid the implicit dev_priv local variable use, and pass dev_priv
> > > explicitly to the ALPM_CTL2 register macro.
> > > 
> > > Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> > > ---
> > >  drivers/gpu/drm/i915/display/intel_psr_regs.h | 2 +-
> > >  1 file changed, 1 insertion(+), 1 deletion(-)
> > > 
> > > diff --git a/drivers/gpu/drm/i915/display/intel_psr_regs.h
> > > b/drivers/gpu/drm/i915/display/intel_psr_regs.h
> > > index 4d950b22d4f1..05dc1c1d4ac2 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_psr_regs.h
> > > +++ b/drivers/gpu/drm/i915/display/intel_psr_regs.h
> > > @@ -321,7 +321,7 @@
> > >  #define 
> > > ALPM_CTL_AUX_LESS_WAKE_TIME(val)              REG_FIELD_PREP(ALPM
> > > _CTL_AUX_LESS_WAKE_TIME_MASK, val)
> > >  
> > >  #define _ALPM_CTL2_A   0x60954
> > > -#define ALPM_CTL2(tran)        _MMIO_TRANS2(dev_priv, tran,
> > > _ALPM_CTL2_A)
> > > +#define ALPM_CTL2(dev_priv, tran)      _MMIO_TRANS2(dev_priv,
> > > tran, _ALPM_CTL2_A)
> > 
> > no usage? should we just delete it?
> 
> I believe a recent addition to enable ALPM. Jouni?

I added it together with other ALPM registers. Currently there is only
one field for LunarLake and we are not changing it from the default. I
would still keep it.

Reviewed-by: Jouni Högander <jouni.hogander@intel.com>


> 
> BR,
> Jani.
> 
> > 
> > >  #define 
> > > ALPM_CTL2_SWITCH_TO_ACTIVE_LATENCY_MASK               REG_GENMASK
> > > (28, 24)
> > >  #define 
> > > ALPM_CTL2_SWITCH_TO_ACTIVE_LATENCY(val)               REG_FIELD_P
> > > REP(ALPM_CTL2_SWITCH_TO_ACTIVE_LATENCY_MASK, val)
> > >  #define 
> > > ALPM_CTL2_AUX_LESS_WAKE_TIME_EXTENSION_MASK           REG_GENMASK
> > > (19, 16)
> > > -- 
> > > 2.39.2
> > > 
>
Jani Nikula May 6, 2024, 8:28 a.m. UTC | #4
On Mon, 06 May 2024, "Hogander, Jouni" <jouni.hogander@intel.com> wrote:
> On Thu, 2024-05-02 at 13:40 +0300, Jani Nikula wrote:
>> On Tue, 30 Apr 2024, Rodrigo Vivi <rodrigo.vivi@intel.com> wrote:
>> > On Tue, Apr 30, 2024 at 01:10:11PM +0300, Jani Nikula wrote:
>> > > Avoid the implicit dev_priv local variable use, and pass dev_priv
>> > > explicitly to the ALPM_CTL2 register macro.
>> > >
>> > > Signed-off-by: Jani Nikula <jani.nikula@intel.com>
>> > > ---
>> > >  drivers/gpu/drm/i915/display/intel_psr_regs.h | 2 +-
>> > >  1 file changed, 1 insertion(+), 1 deletion(-)
>> > >
>> > > diff --git a/drivers/gpu/drm/i915/display/intel_psr_regs.h
>> > > b/drivers/gpu/drm/i915/display/intel_psr_regs.h
>> > > index 4d950b22d4f1..05dc1c1d4ac2 100644
>> > > --- a/drivers/gpu/drm/i915/display/intel_psr_regs.h
>> > > +++ b/drivers/gpu/drm/i915/display/intel_psr_regs.h
>> > > @@ -321,7 +321,7 @@
>> > >  #define
>> > > ALPM_CTL_AUX_LESS_WAKE_TIME(val)              REG_FIELD_PREP(ALPM
>> > > _CTL_AUX_LESS_WAKE_TIME_MASK, val)
>> > >
>> > >  #define _ALPM_CTL2_A   0x60954
>> > > -#define ALPM_CTL2(tran)        _MMIO_TRANS2(dev_priv, tran,
>> > > _ALPM_CTL2_A)
>> > > +#define ALPM_CTL2(dev_priv, tran)      _MMIO_TRANS2(dev_priv,
>> > > tran, _ALPM_CTL2_A)
>> >
>> > no usage? should we just delete it?
>>
>> I believe a recent addition to enable ALPM. Jouni?
>
> I added it together with other ALPM registers. Currently there is only
> one field for LunarLake and we are not changing it from the default. I
> would still keep it.
>
> Reviewed-by: Jouni Högander <jouni.hogander@intel.com>

Thanks for all the reviews, pushed the lot to drm-intel-next.

BR,
Jani.



>
>
>>
>> BR,
>> Jani.
>>
>> >
>> > >  #define
>> > > ALPM_CTL2_SWITCH_TO_ACTIVE_LATENCY_MASK               REG_GENMASK
>> > > (28, 24)
>> > >  #define
>> > > ALPM_CTL2_SWITCH_TO_ACTIVE_LATENCY(val)               REG_FIELD_P
>> > > REP(ALPM_CTL2_SWITCH_TO_ACTIVE_LATENCY_MASK, val)
>> > >  #define
>> > > ALPM_CTL2_AUX_LESS_WAKE_TIME_EXTENSION_MASK           REG_GENMASK
>> > > (19, 16)
>> > > --
>> > > 2.39.2
>> > >
>>
>
diff mbox series

Patch

diff --git a/drivers/gpu/drm/i915/display/intel_psr_regs.h b/drivers/gpu/drm/i915/display/intel_psr_regs.h
index 4d950b22d4f1..05dc1c1d4ac2 100644
--- a/drivers/gpu/drm/i915/display/intel_psr_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_psr_regs.h
@@ -321,7 +321,7 @@ 
 #define  ALPM_CTL_AUX_LESS_WAKE_TIME(val)		REG_FIELD_PREP(ALPM_CTL_AUX_LESS_WAKE_TIME_MASK, val)
 
 #define _ALPM_CTL2_A	0x60954
-#define ALPM_CTL2(tran)	_MMIO_TRANS2(dev_priv, tran, _ALPM_CTL2_A)
+#define ALPM_CTL2(dev_priv, tran)	_MMIO_TRANS2(dev_priv, tran, _ALPM_CTL2_A)
 #define  ALPM_CTL2_SWITCH_TO_ACTIVE_LATENCY_MASK		REG_GENMASK(28, 24)
 #define  ALPM_CTL2_SWITCH_TO_ACTIVE_LATENCY(val)		REG_FIELD_PREP(ALPM_CTL2_SWITCH_TO_ACTIVE_LATENCY_MASK, val)
 #define  ALPM_CTL2_AUX_LESS_WAKE_TIME_EXTENSION_MASK		REG_GENMASK(19, 16)