From patchwork Tue Mar 4 16:29:05 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Lin, Mengdong" X-Patchwork-Id: 3758671 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id A28B5BF13A for ; Tue, 4 Mar 2014 03:27:50 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id DA06B203DF for ; Tue, 4 Mar 2014 03:27:49 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id 22C14203DA for ; Tue, 4 Mar 2014 03:27:49 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 24BF5FB4F6; Mon, 3 Mar 2014 19:27:48 -0800 (PST) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by gabe.freedesktop.org (Postfix) with ESMTP id 55267FB502 for ; Mon, 3 Mar 2014 19:27:41 -0800 (PST) Received: from orsmga001.jf.intel.com ([10.7.209.18]) by orsmga102.jf.intel.com with ESMTP; 03 Mar 2014 19:23:15 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="4.97,582,1389772800"; d="scan'208";a="466083164" Received: from amanda-hsw-pc.sh.intel.com ([10.239.37.140]) by orsmga001.jf.intel.com with ESMTP; 03 Mar 2014 19:27:33 -0800 From: mengdong.lin@intel.com To: intel-gfx@lists.freedesktop.org Date: Tue, 4 Mar 2014 11:29:05 -0500 Message-Id: <0a15819bf2eefe48d874856230d2965ab6539193.1393947538.git.mengdong.lin@intel.com> X-Mailer: git-send-email 1.8.1.2 In-Reply-To: References: Subject: [Intel-gfx] [PATCH 4/7] intel_audio_dump: define get_num_pipes() to get number of pipes for a device ID X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: intel-gfx-bounces@lists.freedesktop.org Errors-To: intel-gfx-bounces@lists.freedesktop.org X-Spam-Status: No, score=-1.0 required=5.0 tests=BAYES_00, DATE_IN_FUTURE_12_24, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=no version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Mengdong Lin It's for future code sharing because some registers define their bit fields according to the number of pipes. Signed-off-by: Mengdong Lin Reviewed-by: Haihao Xiang diff --git a/tools/intel_audio_dump.c b/tools/intel_audio_dump.c index ffd8288..8632ad3 100644 --- a/tools/intel_audio_dump.c +++ b/tools/intel_audio_dump.c @@ -83,6 +83,20 @@ static int disp_reg_base = 0; /* base address of display registers */ #define read_aud_reg(reg) INREG(aud_reg_base + (reg)) +static int get_num_pipes(void) +{ + int num_pipes; + + if (IS_VALLEYVIEW(devid)) + num_pipes = 2; /* Valleyview is Gen 7 but only has 2 pipes */ + else if (IS_G4X(devid) || IS_GEN5(devid)) + num_pipes = 2; + else + num_pipes = 3; + + return num_pipes; +} + static const char * const pixel_clock[] = { [0] = "25.2 / 1.001 MHz", [1] = "25.2 MHz",